Software-Based CCAP Forwarding via Multi-Core DPDK

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Solution Overview

Problem

Current DOCSIS downstream and upstream data forwarding in CCAP environments rely heavily on hardware solutions, limiting flexibility and efficiency, particularly in implementing new features and managing priority data rings.

Innovation Solution

Implementing a software-based Converged Cable Access Platform (CCAP) that utilizes multiple software cores and the Data Path Development Kit (DPDK) for DOCSIS forwarding, employing zero-locking rings and Single Producer Single Consumer rings to manage packet processing and synchronization, allowing for flexible configuration and efficient data handling.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If hardware solutions (TCAMs, FPGAs) are used for DOCSIS forwarding, then forwarding speed and reliability are improved, but flexibility and ease of adding new features deteriorate

Engineering Contradiction:
Improveforwarding reliabilityVSAvoidflexibility to add new features
Core Design Contradiction:
ReliabilityVSAdaptability or versatility

Solution Approach 1:

The patent replaces hardware-based forwarding mechanisms (TCAMs, FPGAs) with a software-based implementation using multiple CPU cores and DPDK. This substitution maintains forwarding reliability through software-based packet processing while gaining flexibility to rapidly add new features and manage priority data rings through software configuration and code updates.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

2Productivity

If hardware solutions are used for DOCSIS forwarding, then forwarding performance is improved, but device complexity and cost increase

Engineering Contradiction:
Improveforwarding performanceVSAvoidsystem complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent uses a multi-core CPU system that can perform multiple functions: DOCSIS forwarding, priority data ring management, and feature implementation. This universal platform replaces specialized hardware components, maintaining high forwarding performance while reducing overall system complexity and eliminating the need for separate TCAM and FPGA devices.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent combines the functions of TCAMs (classification) and FPGAs (packet scheduling and replication) into a unified software-based forwarding plane using multiple CPU cores. This merging consolidates multiple hardware components into a single integrated system, reducing device complexity while maintaining forwarding performance.

Inventive Principle:
Principle #5Merging (Combining)

3Adaptability or versatility

If multiple software cores are used for DOCSIS forwarding, then flexibility and adaptability are improved, but thread synchronization complexity increases

Engineering Contradiction:
ImproveflexibilityVSAvoidsynchronization complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent divides the forwarding workload into separate CPU cores, with each core handling specific DOCSIS forwarding functions. This segmentation allows independent processing on each core, reducing the need for complex inter-thread synchronization while maintaining flexibility through the multi-core architecture.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS11212590B2Multiple core software forwarding
Publication Date: 2021.12.28 HARMONIC INC
  • US11212590B2 patent drawing
  • US11212590B2 patent drawing
  • US11212590B2 patent drawing

AI summary

Approaches for performing all DOCSIS downstream and upstream data forwarding functions using executable software. DOCSIS data forwarding functions may be performed by classifying one or more packets, of a plurality of received packets, to a particular DOCSIS system component, and then processing the one or more packets classified to the same DOCSIS system component on a single CPU core. The one or more packets may be forwarded between a sequence of one or more software stages. The software stages may each be configured to execute on separate logical cores or on a single logical core.