Cycle Count Accurate Transaction Boundary Model for Bus Architecture Simulation
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Solution Overview
Problem
Current System-on-Chip (SoC) design simulation methods, such as pin-accurate Bus Cycle Accurate (PA-BCA) models, are slow and inefficient for complex designs, and while Transaction Level Modeling (TLM) approaches speed up simulation, they do not fully exploit potential for performance exploration due to omitted timing and signal accuracy.
Innovation Solution
The introduction of a Cycle Count Accurate at Transaction Boundaries (CCATB) modeling abstraction level, which bridges the gap between TLM and BCA levels, allowing for faster simulation performance by maintaining cycle count accuracy at transaction boundaries, thereby enabling quicker exploration of communication design spaces.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If pin-accurate Bus Cycle Accurate (PA-BCA) models are used for early communication space exploration, then cycle accuracy is maintained, but simulation speed becomes too slow for complex designs
Solution Approach 1:
The patent segments the simulation model into two distinct levels: a high-level Transaction Level Model (TLM) for fast exploration and a low-level pin-accurate BCA model for verification. This segmentation allows each model to serve its specific purpose without the other's drawbacks, enabling fast initial exploration followed by targeted detailed verification only where needed.
Solution Approach 2:
The patent introduces a new dimension of abstraction by creating an intermediate TLM layer above the traditional BCA model. This additional abstraction dimension allows designers to explore communication spaces at a higher level of generality before committing to detailed cycle-accurate models, effectively adding a temporal dimension to the modeling hierarchy.
2Productivity
If Transaction Level Modeling (TLM) approaches are used to speed up simulation, then simulation performance improves, but timing and signal accuracy are omitted reducing exploration reliability
Solution Approach 1:
The patent implements a dynamic modeling approach where the level of detail is adjusted based on the exploration phase. During early communication space exploration, the system uses coarse-grained TLM for speed. When specific architectures show promise or performance boundaries need verification, the model dynamically refines to BCA level, adapting the simulation fidelity to the current design needs.
Solution Approach 2:
The patent introduces an intermediary refinement process that bridges TLM and BCA models. This intermediary layer allows seamless transition between abstraction levels, enabling designers to start with fast TLM exploration and progressively refine specific communication paths to BCA accuracy only where necessary, rather than maintaining full accuracy throughout the entire system.
3Manufacturing precision
If RTL level modeling is used for bus-based communication architectures, then detailed accuracy is achieved, but re-engineering effort increases considerably when making design changes
Solution Approach 1:
The patent applies preliminary action by performing communication space exploration and performance evaluation at the high-level TLM stage before committing to detailed RTL implementation. This allows designers to identify optimal communication architectures and parameters early, so that when RTL design begins, the architecture is already well-established, minimizing subsequent re-engineering efforts.
Solution Approach 2:
The patent uses partial action by applying detailed BCA modeling only to specific communication paths that require verification, rather than modeling the entire system at BCA level. This selective refinement approach maintains design accuracy where needed while avoiding the excessive re-engineering effort that would result from comprehensive detailed modeling throughout the design process.
Data Source
AI summary
A computer system simulation method starts with algorithmically implementing a specification model independently of hardware architecture. High level functional blocks representing hardware components are connected together using a bus architecture-independent generic channel. The bus architecture-independent generic channel is annotated with timing and protocol details to define an interface between the bus architecture-independent generic channel and functional blocks representing hardware components. The interface is refined to obtain a CCATB for communication space. The read( ) and write( ) interface calls are decomposed into several method calls which correspond to bus pins to obtain observable cycle accuracy for system debugging and validation and to obtain a cycle accurate model. The method calls are replaced by signals, and the functional blocks representing hardware components are further refined to obtain pin/cycle-accurate models which can be manually or automatically mapped to RTL, or be used to co-simulate with existing RTL components.