CCD Transimpedance Amplifier Layout for Low-Noise Charge Readout
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Solution Overview
Problem
CCD imaging devices face limitations in low light applications due to high parasitic capacitance and noise from off-chip amplifiers, which restricts charge-transfer efficiency and signal gain, as CMOS and CCD fabrication processes are incompatible, leading to imperfections in semiconductor materials and limited circuitry capabilities.
Innovation Solution
A hybrid image sensor design where part of the amplifier is on the CCD chip, using FETs fabricated in the CCD system, and the other part utilizes CMOS or bipolar components off-chip, with a capacitor network and switch configuration to minimize parasitic capacitance and noise, and adjustable feedback capacitance to adapt to light conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If an off-chip amplifier is used to amplify small charge signals from pixels, then signal gain is improved, but parasitic capacitance and noise increase, limiting maximum gain
Solution Approach 1:
The amplifier is divided into two parts: an on-chip transimpedance amplifier stage that performs initial charge-to-voltage conversion and amplification, and an off-chip buffer stage that provides additional gain without adding significant parasitic capacitance to the sensitive input node. This segmentation allows the system to achieve high overall gain while minimizing the parasitic capacitance penalty that would result from using a single off-chip amplifier.
2Manufacturing precision
If CCD fabrication processes are used to ensure high charge-transfer efficiency, then manufacturing precision is improved, but device complexity increases and compatibility with CMOS logic circuitry is reduced
Solution Approach 1:
The imaging device is segmented into a CCD array portion fabricated using specialized CCD processes to ensure high charge-transfer efficiency, and a logic circuitry portion fabricated using standard CMOS processes. The two portions are integrated into a single hybrid device, allowing each to be optimized for its specific function while achieving overall system compatibility and reduced fabrication complexity.
3Ease of manufacture
If a large pad area is used to connect the amplifier to the substrate via solder bump, then ease of manufacture is improved, but parasitic capacitance increases, reducing maximum gain
Solution Approach 1:
The sensitive input node of the amplifier is extracted and isolated from the large substrate connection pad by placing it on a small isolated island surrounded by guard rings. This extraction ensures that the parasitic capacitance associated with the large pad area does not affect the amplifier's input node, allowing the system to maintain both ease of manufacture through large pads and high maximum gain through minimized input parasitic capacitance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances low light performance by reducing noise and increasing signal gain, allowing for more efficient charge conversion and amplification while maintaining compatibility between CMOS and CCD fabrication processes.
Implementation Method 1
A first capacitor on the first substrate connects the node to a second conducting pad on the first substrate
Implementation Method 2
a first FET fabricated on the first substrate in the first fabrication system, the first FET having a gate connected to the node and a source or drain connected to a first conducting pad on the first substrate
Implementation Method 3
A first switch fabricated on the first substrate in the first fabrication system is connected across the first capacitor such that the first capacitor is shorted when the first switch is closed
Data Source
AI summary
An image sensor having a first substrate on which a CCD array is fabricated in a first fabrication system is disclosed. The CCD array includes a node through which charge from the pixels passes during a readout operation. The first substrate also includes a first FET fabricated on the first substrate in the first fabrication system, the first FET having a gate connected to the node and a source or drain connected to a first conducting pad on the first substrate. A capacitor connects the node to a second conducting pad on the first substrate. A switch is connected across the first capacitor such that the first capacitor is shorted when the first switch is closed. The first switch is controlled by a reset signal on a third conducting pad on the first substrate. The first substrate can be connected to a second substrate having amplification and control circuitry.