CCD/CIS Analog Frontend With Cyclic ADC and Flash Residue Conversion
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Solution Overview
Problem
Existing systems for processing charge coupled device (CCD) or contact image sensor (CIS) analog data require a large number of components and consume significant power, making them inefficient for high-resolution image data processing.
Innovation Solution
A cyclic analog to digital converter structure with multiple stages is implemented, where each stage performs 1.5 bits of conversion, with feedback to iteratively generate most significant bits, and a flash ADC generates the least significant bits, integrating offset DAC as part of the ADC stages to reduce power and area, and using dynamic current scaling to minimize total power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If existing systems process CCD/CIS sensor analog data, then data conversion is achieved, but the number of system components increases and power consumption increases
Solution Approach 1:
The patent combines multiple previously separate functions (sampling, offset correction, gain control, and ADC conversion) into a single integrated cyclic ADC structure. The first stage performs sampling, single-ended to differential conversion, and coarse/fine offset correction, while the second stage performs iterative 1.5-bit/stage ADC conversion with feedback. This integration reduces the number of discrete components while maintaining high conversion precision through the coordinated operation of these combined functions.
Solution Approach 2:
The cyclic ADC structure serves multiple functions simultaneously: the first stage acts as a sampler, offset corrector, and differential converter, while the second stage performs iterative ADC conversion. The feedback mechanism allows the system to achieve high-resolution conversion (N-bit) by combining 1.5-bit/stage iterations with a final 3-bit flash ADC, making the system universally capable of high-precision analog-to-digital conversion without requiring separate dedicated components for each function.
2Measurement precision
If existing systems process CCD/CIS sensor analog data, then data conversion is achieved, but power consumption increases
Solution Approach 1:
The patent implements dynamic current scaling in the cyclic ADC structure to minimize power consumption. The system adaptively adjusts the operating current of the second stage based on the conversion requirements and feedback from previous iterations. During the iterative 1.5-bit/stage conversion process, the current is dynamically scaled down when full precision is not yet required, and only increased when necessary to achieve the final N-bit resolution, thereby significantly reducing overall power consumption while maintaining conversion precision.
Solution Approach 2:
The cyclic ADC structure employs periodic operation where the second stage performs iterative 1.5-bit conversions in a cyclic manner with feedback to the first stage. This periodic action allows the system to gradually build up the N-bit resolution over multiple cycles rather than requiring continuous high-power operation, enabling precision to be achieved through repeated low-power iterations followed by a final 3-bit flash ADC conversion.
3Use of energy by stationary object
If cyclic ADC structure with iterative conversion is used, then power consumption is reduced, but conversion time increases
Solution Approach 1:
The patent segments the ADC conversion process into three distinct parts: (1) the first stage performing sampling and offset correction, (2) the second stage performing iterative 1.5-bit/stage conversion for the (N-3) most significant bits, and (3) a final 3-bit flash ADC for the least significant bits. This segmentation allows the time-consuming iterative process to be limited to only the most significant bits, while the flash ADC quickly resolves the least significant bits in parallel, thereby reducing total conversion time while maintaining the power-saving benefits of the iterative approach for the majority of bits.
Solution Approach 2:
The system changes the conversion approach based on bit significance: using iterative 1.5-bit/stage conversion with feedback for the (N-3) most significant bits where precision is critical, and switching to a parallel 3-bit flash ADC for the least significant bits where speed is more important. This parameter change in conversion methodology optimizes the trade-off between power consumption and conversion time by applying the most efficient method for each bit group.
Data Source
AI summary
A system for signal processing comprising a cyclic analog to digital converter structure having a first stage and a second stage, wherein the first stage is configured to receive an input signal to perform 1.5 bits/stage ADC and to generate a first stage output signal, and the second stage is configured to receive the first stage output signal and to perform fine offset tuning using a final conversion phase. The second stage further configured to perform 1.5 bits/stage ADC and to generate a second stage output that is fed back to the first stage to iteratively generate a next 1.5 bits, until (N−3) most significant bits of N bits of data are generated. A third stage configured to generate a three least significant bits of the N bits of data using a flash ADC sampling circuit that samples a residue signal at the output of the first stage.