Solid-State Image Pickup Device Charge Transfer Timing Control
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Solution Overview
Problem
In three-line solid-state image pickup devices with a two-line pixel row spacing, charge blooming occurs due to overlapping vertical transfer pulse timing, leading to charge leakage and reduced saturated charge amounts in CCD registers, which can be mitigated but at the cost of increased vertical transfer time.
Innovation Solution
The implementation of a control pulse timing scheme where the Hi periods of first and second control pulses do not overlap during vertical transfer, ensuring charges are transferred without blooming and maintaining efficient transfer times by configuring the CK1 and CK2 pulses to avoid overlap, thereby preventing charge leakage to prior pixels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If vertical transfer pulse timing is adjusted to avoid blooming, then charge leakage is prevented, but vertical transfer time increases
Solution Approach 1:
The patent applies dynamics by making the control pulse timing adjustable and adaptable. The system dynamically configures the Hi period timing of CK1 and CK2 pulses based on operating conditions, allowing optimal prevention of blooming while minimizing transfer time. This dynamic adjustment resolves the contradiction by enabling the system to adapt its timing characteristics rather than being fixed.
Solution Approach 2:
The patent changes the timing parameters of control pulses CK1 and CK2, specifically the Hi period duration and positioning. By optimizing these parameters so that Hi periods do not overlap during vertical transfer, the system prevents blooming while maintaining efficient transfer timing. This parameter optimization resolves the contradiction between preventing charge leakage and maintaining fast transfer.
2Reliability
If control pulses are configured to prevent blooming, then saturated charge amount is maintained, but device complexity increases
Solution Approach 1:
The patent makes the control pulse timing configuration universal by designing a timing scheme that works across different operating conditions and charge amounts. The same Hi period non-overlapping configuration of CK1 and CK2 pulses effectively prevents blooming regardless of the specific imaging conditions, eliminating the need for complex conditional control logic and reducing overall device complexity.
Data Source
AI summary
A solid-state image pickup device according to an embodiment is a solid-state image pickup device including a first pixel row, a second pixel row, and a third pixel row that are arranged in a horizontal direction. In the solid-state image pickup device, a first control pulse for transferring charges of first accumulation portions of the fourth and sixth CCD registers in a vertical direction perpendicular to the horizontal direction and a second control pulse for transferring charges of second accumulation portions of the fourth and sixth CCD registers in the horizontal direction are input to the fourth and sixth CCD registers such that an Hi period of the first control pulse and an Hi period of the second control pulse do not overlap each other in a timing period in which charges accumulated in the first, second, and third pixel rows are transferred.