Custom Control Data Register Scan Path Design

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

The integration of test-related hardware in digital systems often results in untested nodes due to its own complexity, making it difficult to achieve high test coverage percentages, especially in industries with stringent reliability requirements like automotive and aerospace.

Innovation Solution

The implementation of custom scan cells with enhanced testability, including custom control data registers (CCDR) and dynamic control data registers (CDCDR) circuits, which provide a modified scan cell structure with increased testability by using shift registers and update registers configured to receive and output scan data, enabling comprehensive testing in compliance with standards like IEEE 1149.x and 1500.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If test-related hardware is integrated into digital systems to enable testing, then testing capability is improved, but the test hardware itself becomes complex and creates untested nodes reducing test coverage

Engineering Contradiction:
Improvetest coverageVSAvoidtest hardware complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The scan cell is designed to perform multiple functions: it enables boundary scan operations for testing while also functioning as a regular control data register during normal operation. The same hardware structure supports both test mode (scan chain operation) and normal mode (data register operation), eliminating the need for separate test hardware and thereby improving test coverage without proportionally increasing complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent merges the test functionality (scan chain) with the functional register (control data register) into a single integrated structure. The scan cell combines the scan flip-flop for test operations with the functional register logic, allowing the hardware to serve dual purposes and reducing the overall complexity burden of having separate test and functional components.

Inventive Principle:
Principle #5Merging (Combining)

2Ease of operation

If standard scan cells are used for boundary scan testing, then basic testing capability is provided, but comprehensive testing of all nodes including the scan cell itself is difficult to achieve

Engineering Contradiction:
Improvetesting capabilityVSAvoidtest coverage
Core Design Contradiction:
Ease of operationVSReliability

Solution Approach 1:

The control data register is segmented into multiple scan cells that can be individually tested. Each scan cell represents a discrete unit that can be independently controlled and observed through the scan chain, allowing systematic testing of each portion of the register. This segmentation enables complete coverage of all nodes within the register structure.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The scan chain acts as an intermediary mechanism that provides access to all internal nodes of the control data register. By inserting scan cells at strategic positions within the register structure, the scan chain enables observation and control of internal nodes that would otherwise be inaccessible, thereby achieving comprehensive test coverage without requiring direct access to each individual node.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS11680984B1Control data registers for scan testing
Publication Date: 2023.06.20 TEXAS INSTRUMENTS INC
  • US11680984B1 patent drawing
  • US11680984B1 patent drawing
  • US11680984B1 patent drawing

AI summary

In some examples, a circuit includes a custom control data register (CCDR) circuit having a scan path. The CCDR circuit includes a shift register and an update register. The shift register is configured to receive scan data from a scan data input (CDR_SCAN_IN) on a first clock edge responsive to a scan enable signal (CDR_SCAN_EN) being enabled. The update register is configured to receive data from the shift register on a second clock edge after the first clock edge when the scan enable (CDR_SCAN_EN) is enabled. The update register data is asserted as a scan data output (CDR_SCAN_OUT). The second scan path includes the scan data input, the shift register, the update register, and the scan data output.