CCII Second-Order All-Pass Network With Tunable Delay Q
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing second-order all-pass networks face challenges in achieving high delay Q-values on-chip due to non-ideal Current Conveyor (CCII) parameters and resonant losses, which are not effectively addressed by current designs, limiting their practicality for high-bandwidth applications.
Innovation Solution
A second-order all-pass network is synthesized using three CCIIs with a tunable RC network implemented in 0.35 μm CMOS technology, incorporating varactors and NMOS transistors operating in the triode region, allowing for post-production tuning to compensate for CCII non-idealities and process variations, thereby achieving a delay Q-value larger than 1.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If passive lumped element configurations are used on-chip, then the network can be integrated, but resonant loss increases due to low inductor Q-factors
Solution Approach 1:
The patent replaces passive mechanical inductors with an active inductorless CMOS circuit implementation using CCIIs. This substitution eliminates the fundamental limitation of on-chip inductor Q-factors (typically less than 10) while maintaining on-chip integrability. The active circuit synthesizes the required inductive behavior through transistor switching and capacitive elements, achieving effective Q-factors greater than 1 without requiring physical inductors.
2Manufacturing precision
If op-amp based realizations are used, then Q-values larger than 1 can be achieved, but bandwidth is reduced
Solution Approach 1:
The patent changes the fundamental operating parameters by using CCIIs instead of op-amps. CCIIs operate with current-mode signaling and different feedback mechanisms that inherently provide higher bandwidth compared to voltage-mode op-amp implementations. The circuit achieves Q-values greater than 1 through precise control of capacitive ratios and transistor sizing, while the current-mode operation maintains bandwidth superiority over traditional op-amp based designs.
3Device complexity
If CCII non-idealities are not compensated, then the circuit design is simpler, but performance degrades with magnitude peaks and notches
Solution Approach 1:
The patent incorporates feedback mechanisms through the inherent structure of CCIIs and additional feedback paths in the circuit topology. The CCIIs provide natural feedback through their current conveyor operation, and the circuit design includes specific feedback capacitors and resistors that compensate for non-idealities. This feedback approach stabilizes the magnitude response by actively correcting deviations caused by non-unity voltage mirroring and current conveying, eliminating magnitude peaks and notches while maintaining reasonable design complexity.
4Ease of manufacture
If process parameter variation is not accounted for, then manufacturing is easier, but the circuit performance varies due to CCII parameter changes
Solution Approach 1:
The patent implements dynamic compensation through post-production tuning capabilities. The circuit includes tunable elements such as variable capacitors or switched capacitor networks that allow adjustment of circuit parameters after manufacturing. This dynamic adjustment capability enables compensation for process variations and CCII parameter changes, ensuring consistent performance across different manufacturing batches and operating conditions while maintaining relatively simple manufacturing processes.
Data Source
AI summary
A second-order all-pass network has at least three Second Generation Current Conveyors (CCIIs). A network input is connected or connectable to a Y port of a first CCII, a Z port of the first CCII is connected to a Y port of a second CCII, an X port of the first CCII is connected to a Y port of a third CCII, and a network output is connected or connectable, directly or indirectly, to a Z port of the second CCII. The X port of the first CCII is connected via a first network element to ground, the Z port of the first CCII is connected via a second network element to ground, an X port of the third CCII is connected via a third network element to ground, and an X port of the second CCII is connected via a fourth network element to ground.