CCK Demodulation with Decision Feedback for Multipath Interference
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Solution Overview
Problem
Higher data rate wireless communication systems, such as IEEE 802.11b, face challenges in demodulating CCK symbols due to multipath reflections, which cause bit errors and require complex filtering to compensate for channel variations, especially at 5.5 Mb and 11 Mb data rates, where the channel is more susceptible to interference.
Innovation Solution
A CCK symbol demodulator that employs decision feedback equalization and maximum likelihood estimation to correct inter-symbol interference by subtracting previous symbol effects from current symbols, using a post-equalization value generator and feedback filters to improve demodulation accuracy, and a reduced complexity implementation with fewer taps to minimize computational complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a channel matched filter with many taps is used to compensate for multipath reflections, then demodulation accuracy is improved, but device complexity increases
Solution Approach 1:
The patent divides the channel compensation function into two separate filters: a feed-forward filter (FFF) that handles pre-cursor interference from previous symbols, and a decision feedback filter (DFE) that handles post-cursor interference. This segmentation allows each filter to have fewer taps while collectively providing the same level of multipath compensation, thereby reducing individual filter complexity while maintaining demodulation accuracy.
Solution Approach 2:
The patent implements a decision feedback mechanism where previously demodulated symbols are fed back through the DFE to cancel out post-cursor interference from multipath reflections. This feedback approach allows the system to use fewer filter taps compared to a pure feed-forward equalizer, as the feedback path efficiently removes residual interference after initial FFF processing, thus reducing overall device complexity while maintaining accuracy.
2Reliability
If the number of filter taps is increased to handle higher data rates, then reliability is improved, but computational complexity increases
Solution Approach 1:
The patent segments the equalization process into feed-forward and feedback components, each with optimized tap counts suitable for high data rate operation. The FFF uses a limited number of taps to address pre-cursor effects, while the DFE handles post-cursor effects through feedback, collectively providing sufficient reliability for 5.5 Mb and 11 Mb data rates without requiring a single complex filter with many taps, thus controlling computational complexity.
Solution Approach 2:
The patent optimizes the tap counts for both FFF and DFE specifically for high data rate CCK demodulation, adjusting the filter parameters to achieve the minimum necessary complexity for reliable operation at 5.5 Mb and 11 Mb. This parameter optimization ensures that the filters provide adequate reliability for high data rates while minimizing computational complexity by using only the necessary number of taps.
3Reliability
If channel sounding is performed to characterize the communications channel, then demodulation reliability is improved, but loss of time occurs during training
Solution Approach 1:
The patent performs channel sounding during the preamble portion of the transmitted signal, which occurs before the actual data transmission begins. This preliminary characterization of the channel allows the receiver to pre-compute the FFF and DFE coefficients needed for accurate demodulation, ensuring reliability is improved while the time loss is confined to the preamble period rather than affecting data transmission time.
Data Source
AI summary
A maximum likelihood CCK detector has a first subtractor which subtracts the contents of a pre-equalize register from a current symbol, and the output of this subtractor is coupled to a simple Fast Walsh Transform (FWT) with an iteration variable k. The output of the FWT is coupled to a second subtractor for subtracting a plurality of ICI corrections for all possible current symbols computed from the post-FWT domain value of the current CCK symbol and stored in post equalization registers. A post equalization register contains values computed from feedback filter coefficients determined during a packet preamble, where the feedback filter coefficients are provided to a reduced complexity post equalization value generator which populates the post equalization register using an iteration variable i.