CD Trimming SiARC and Planarization Layers

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Solution Overview

Problem

Current methods for critical dimension (CD) trimming in substrate processing often result in final patterns with unacceptable line edge roughness (LER) and line width roughness (LWR) values, leading to structure pattern collapse and unusability, especially when the final CD target is smaller than the printed CD target, and there is a need for an approach to achieve an acceptable CD range throughout multiple integration stages.

Innovation Solution

A method for CD trimming that involves providing a substrate with SiARC or SiON layers and an optical planarization layer, performing optional CD trimming processes, and concurrently controlling operating variables such as gas flowrate and exposure time using online metrology to achieve precise CD trimming, with the planarization layer being one of an advanced patterning film (APF), organic dielectric layer (ODL), or spin-on hardmask (SOH) layer.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If conventional plasma trimming process is used to reduce final CD target, then the printed CD target can be larger, but the line edge roughness (LER) and line width roughness (LWR) values become unacceptable leading to pattern collapse

Engineering Contradiction:
Improvecritical dimension (CD)VSAvoidline edge roughness (LER) and line width roughness (LWR)
Core Design Contradiction:
Manufacturing precisionVSReliability

Solution Approach 1:

The patent segments the CD trimming process into multiple discrete stages: (1) initial resist pattern formation, (2) SiARC/SiON layer opening with first CD trim, (3) optical planarization layer opening with second CD trim, and (4) final pattern transfer. Each stage performs a portion of the total required CD reduction, distributing the trimming load to prevent excessive roughness at any single stage while achieving the final target CD.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent performs preliminary CD trimming during the SiARC/SiON layer opening stage before completing the optical planarization layer opening. This preliminary action reduces the CD burden for subsequent stages, enabling the final pattern to achieve the target CD without requiring excessive trimming in the last stage that would cause pattern collapse.

Inventive Principle:
Principle #10Preliminary action

2Manufacturing precision

If multiple stages of CD trimming are performed, then the final target CD can be achieved within acceptable range, but the process complexity increases

Engineering Contradiction:
Improvefinal target CDVSAvoidprocess complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent merges CD trimming operations with existing pattern transfer stages. Instead of adding separate dedicated trim steps, the CD trimming is integrated into the SiARC/SiON opening process and the optical planarization layer opening process. This combining approach achieves multi-stage CD control without proportionally increasing process complexity, as each stage serves dual purposes of layer removal and CD adjustment.

Inventive Principle:
Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively trims the CD to achieve acceptable LER and LWR values, ensuring the final structure pattern meets the target CD range, with the ability to trim in multiple stages and using online metrology for real-time adjustments, thereby preventing pattern collapse and enhancing substrate usability.

Implementation Method 1

This invention relates to structure patterning using a plasma trimming process

Methodology Applied
Scientific EffectPlasma: Plasma

Data Source

PatentUS10049875B2Trim method for patterning during various stages of an integration scheme
Publication Date: 2018.08.14 TOKYO ELECTRON LTD
  • US10049875B2 patent drawing
  • US10049875B2 patent drawing
  • US10049875B2 patent drawing

AI summary

Provided is a method for critical dimension (CD) trimming of a structure pattern in a substrate, the method comprising: providing a substrate in a process chamber of a patterning system, the substrate comprising a first structure pattern and an underlying layer, the underlying layer comprising a silicon anti-reflective coating (SiARC) or a silicon oxynitride (SiON) layer, an optical planarization layer, and a target patterning layer; performing an optional CD trimming process of the first structure pattern; performing a series of processes to open the SiARC or SiON layer and performing additional CD trimming if required; and performing a series of processes to open the optical planarization layer, the series of processes generating a final structure pattern, and performing additional CD trimming if required; wherein the planarization layer is one of a group comprising an advance patterning film (APF), an organic dielectric layer (ODL) or a spin-on hardmask (SOH) layer.