CDAC Capacitive References for Fast Settling and Lower Power
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Solution Overview
Problem
Capacitive Digital to Analog Converters (CDACs) face challenges in quickly converting digital data to analog signals, resulting in significant power dissipation due to the high current required for charging capacitors, which is undesirable, especially in asynchronous-timed Successive-Approximation Register (SAR) Analog to Digital Converters (ADCs).
Innovation Solution
Implementing individual reference capacitors for each input capacitor to provide reference voltages, allowing for smaller capacitors and faster settling speeds while reducing power dissipation, as opposed to using a single global capacitive reference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If a single global capacitive reference is used to charge all input capacitors, then the charging operation can be performed, but significant current is drawn causing high power dissipation
Solution Approach 1:
The patent divides the single global capacitive reference into multiple individual reference capacitors, with each reference capacitor dedicated to charging a specific input capacitor. This segmentation allows each capacitor to be charged independently with smaller current, reducing overall power dissipation while maintaining charging functionality.
2Speed
If larger capacitors are used to store more charge, then the charging capacity increases, but the settling speed decreases
Solution Approach 1:
By segmenting the total capacitance into multiple smaller reference capacitors, each capacitor can be sized optimally for its specific function. This allows the system to achieve fast settling speeds with smaller individual capacitors while collectively providing sufficient charging capacity for all input capacitors.
Solution Approach 2:
The patent transitions from a single-dimension approach (one large global reference capacitor) to a multi-dimensional approach (multiple smaller reference capacitors distributed across different locations in the circuit). This dimensional change enables parallel charging operations, improving settling speed without requiring large individual capacitor sizes.
3Productivity
If significant current is drawn to charge capacitors quickly, then the charging speed increases, but power dissipation increases
Solution Approach 1:
The patent segments the charging operation into multiple parallel operations, each handling a portion of the total charging load. This allows the system to achieve high overall charging speed through parallelism while each individual operation uses smaller current, thereby reducing power dissipation.
Solution Approach 2:
The patent implements periodic charging cycles where reference capacitors are charged and discharged in a coordinated sequence. This periodic action allows for efficient charge transfer with reduced peak current requirements, balancing charging speed with power consumption.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables faster settling and lower power dissipation by using smaller capacitors, improving the efficiency of CDACs in converting digital data to analog signals.
Implementation Method 1
a first reference capacitor coupled to the first input capacitor and configured to provide a reference voltage to the first input capacitor
Data Source
AI summary
Disclosed are circuits and methods for a CDAC with capacitive references. Individual reference capacitors can be implemented to provide the reference voltages for each input capacitor in a CDAC. For example, each input capacitor may be allocated a high-reference capacitor and a low-reference capacitor to provide the reference voltage to the respective input capacitor. Each of these reference capacitors is charged along with the input capacitor when the CDAC is configured into a loading configuration, and then used to convert digital data to an analog signal when the CDAC is configured into a conversion configuration. Accordingly, the reference voltage for each input capacitor is provided by a separate power source. This contrasts with current solutions in which the reference voltages for the input capacitors are provided by either a singular high-reference voltage source or low-reference voltage source.