Capacitive DAC DTC Architecture for Constant-Slope Delay Linearity
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Solution Overview
Problem
Constant slope digital-to-time converters (DTCs) face challenges in achieving high linearity due to variable delay element slopes, which can be exacerbated by the need for separate charging capacitors that increase the DTC profile and introduce non-linearity sources like charge injection and clock feedthrough, particularly in low noise applications such as 5G communication systems.
Innovation Solution
A digital-to-time converter (DTC) circuit incorporating a capacitive digital-to-analog converter (CDAC) that functions as both a DAC and a charging capacitor, generating input control word dependent voltages to produce a constant slope ramp voltage, thereby reducing the DTC profile and complexity, and improving linearity by eliminating the need for a separate charging capacitor and simplifying switching methods.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a separate charging capacitor is used in constant slope DTC, then the DTC can generate voltage ramp, but the DTC profile increases and non-linearity sources (charge injection, clock feedthrough) are introduced
Solution Approach 1:
The patent merges the charging capacitor function with the DAC capacitor by having the DAC capacitor serve dual purposes: generating the input control word dependent voltage and functioning as the charging capacitor for the voltage ramp. This eliminates the need for a separate charging capacitor, reducing the DTC profile and removing non-linearity sources associated with additional switching components.
Solution Approach 2:
The DAC capacitor is designed to perform multiple functions: it generates the input control word dependent voltage during the DAC operational phase and simultaneously serves as the charging capacitor during the charging phase. This multi-functionality reduces the total component count and eliminates the need for separate charging capacitor switches that introduce non-linearity.
2Ease of operation
If multiple switches are used for charging and discharging, then the DTC can control voltage ramp generation, but non-linear sources like charge injection and clock feedthrough increase
Solution Approach 1:
The patent extracts and eliminates the separate charging capacitor and its associated switches from the DTC architecture. By using only the DAC capacitor for charging, the design removes the charging capacitor switches that are sources of charge injection and clock feedthrough non-linearity, while maintaining voltage ramp control through the existing DAC switching mechanism.
Solution Approach 2:
The patent converts the potential harm of using the DAC capacitor for dual purposes into a benefit by eliminating the need for additional switches. The DAC switching mechanism, already optimized for digital control, is used for charging operations, avoiding the introduction of new non-linear sources while maintaining precise voltage ramp control.
3Adaptability or versatility
If separate charging capacitor and DAC are used, then the DTC can generate input control word dependent voltage, but the device complexity and profile increase
Solution Approach 1:
The patent combines the DAC and charging capacitor into a single component - the DAC capacitor. This capacitor generates the input control word dependent voltage when connected to the DAC output and simultaneously serves as the charging capacitor when connected to the charging current source, eliminating the need for separate components and reducing overall device complexity.
Solution Approach 2:
The DAC capacitor is designed with multi-functionality to generate input control word dependent voltage and serve as the charging capacitor. By using the same physical capacitor for both purposes and controlling its connections through switching, the patent reduces component count while maintaining full functionality for voltage ramp generation with programmable delay.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances the linearity and reduces the profile of the DTC, improving its performance in applications like fractional-N phase-locked loop designs by minimizing non-linear sources and phase noise, thus meeting the stringent requirements of 5G communication standards.
Implementation Method 1
a first switch connected between a first power source and a second node, and configured to provide a charge current to the second node
Implementation Method 2
The DAC circuit is configured to be charged to generate a voltage ramp corresponding to the charge current during a first DTC operational phase, and to generate an input control word dependent voltage according to an input control word during a second DTC operational phase
Implementation Method 3
generating input control word dependent voltages to produce a constant slope ramp voltage
Data Source
AI summary
A DTC circuit, includes: a DAC connected to a first node; a first switch connected between a first power source and a second node, and to provide a charge current to the second node according to a first switching signal; and a second switch connected between the first node and the second node, and to electrically connect the DAC to the second node according to a second switching signal. The DAC is to be charged to generate a voltage ramp corresponding to the charge current during a first DTC operational phase when the first and second switching signals have an active level to turn on the first and second switches, and to generate an input control word dependent voltage according to an input control word during a second DTC operational phase when the first and second switching signals have an inactive level to turn off the first and second switches.