Clock Domain Crossing Buffering for Propagation Delay Simulation
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Solution Overview
Problem
Clock domain crossing in integrated circuits leads to timing issues such as metastability and data loss due to miscoordination of clock signals, which are often detected after fabrication, increasing design costs and implementation time.
Innovation Solution
Incorporating signal path information and timing parameters into configuration files and RTL models to simulate and manage propagation delays, allowing for the insertion of buffers to coordinate clock signals and prevent timing problems during the design stages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If clock domain crossing is implemented without propagation delay simulation, then design implementation speed is improved, but timing problems such as metastability and data loss occur
Solution Approach 1:
The patent applies preliminary action by performing propagation delay simulation during the design stage using RTL models and configuration files. Timing parameters are added to configuration files before fabrication, allowing timing problems to be detected and corrected in advance, rather than discovering them after manufacturing.
Solution Approach 2:
The patent creates a virtual copy of the physical circuit through RTL models that replicate the behavior of the actual hardware. Configuration files serve as a digital representation containing timing parameters, allowing simulation of propagation delays without requiring physical prototypes or fabricated chips.
2Measurement precision
If propagation delay simulation is performed using detailed timing parameters, then timing problem detection accuracy is improved, but design complexity increases
Solution Approach 1:
The patent introduces configuration files as an intermediary layer between the RTL model and the physical implementation. These files contain timing parameters that mediate between the abstract design and concrete timing characteristics, enabling accurate simulation without directly complicating the RTL design process itself.
Solution Approach 2:
The patent segments the design process into distinct components: RTL models for functional verification, configuration files for timing parameters, and simulation tools for analysis. This segmentation allows each component to be developed and verified independently, reducing overall design complexity while maintaining high detection accuracy.
3Reliability
If buffers are inserted to coordinate clock signals, then clock signal coordination is improved, but device complexity increases
Solution Approach 1:
The patent identifies paths requiring buffer insertion through propagation delay simulation during the design stage. By detecting timing violations beforehand, buffers can be strategically placed only where necessary, rather than adding buffers throughout the entire circuit. This preliminary identification minimizes the number of buffers needed while ensuring adequate clock signal coordination.
Data Source
AI summary
Techniques are disclosed relating to detecting and minimizing timing problems created by clock domain crossing (CDC) in integrated circuits. In various embodiments, one or more timing parameters are associated with a path that crosses between clock domains in an integrated circuit, where the one or more timing parameters specify a propagation delay for the path. In one embodiment, the timing parameters may be distributed to different design stages using a configuration file. In some embodiments, the one or more parameters may be used in conjunction with an RTL model to simulate propagation of a data signal along the path. In some embodiments, the one or more parameters may be used in conjunction with a netlist to create a physical design for the integrated circuit, where the physical design includes a representation of the path that has the specified propagation delay.