Continuous Diffusion Bridged Cell Library for Leakage Reduction

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Solution Overview

Problem

In modern integrated circuit design, transistor performance is influenced by breaks in the diffusion area, which affect leakage power and overall performance due to stress differences and localized heating during fabrication processes, limiting the effectiveness of existing cell architectures.

Innovation Solution

The introduction of a cell architecture with continuous diffusion regions and polysilicon gates that allow for bridging of cells, enabling continuous diffusion between transistors while maintaining electrical isolation, and the use of filler cells and end-cap cells to optimize diffusion profiles and reduce leakage power.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If diffusion is broken at cell edges for electrical isolation, then electrical isolation between cells is improved, but transistor performance deteriorates due to loss of LOD effects

Engineering Contradiction:
Improveelectrical isolationVSAvoidtransistor performance
Core Design Contradiction:
ReliabilityVSPower

Solution Approach 1:

The cell library is segmented into two types: cells with broken diffusion for electrical isolation and cells with continuous diffusion for performance optimization. This segmentation allows the system to achieve both electrical isolation and transistor performance by distributing different diffusion configurations across the library.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The invention creates a universal cell library architecture that can function in both isolated and continuous diffusion modes. Cells are designed with flexible diffusion structures that can be configured based on whether they need to provide electrical isolation or maintain LOD effects for performance, making the library adaptable to different functional requirements.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Ease of manufacture

If uniform diffusion pattern is used in gate-array, then manufacturing simplicity is improved, but diffusion size optimization deteriorates as all logic circuits have similar diffusion sizes

Engineering Contradiction:
Improvediffusion patterning simplicityVSAvoiddiffusion size optimization
Core Design Contradiction:
Ease of manufactureVSAdaptability or versatility

Solution Approach 1:

Instead of uniform diffusion patterning, the invention applies local quality by allowing diffusion size and continuity to vary based on the specific requirements of each logic circuit. Different cells can have optimized diffusion dimensions tailored to their functional needs while maintaining overall manufacturing feasibility.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The cell library employs dynamic diffusion configurations where diffusion continuity and sizing can be adjusted based on circuit requirements. Rather than a fixed uniform pattern, the system allows diffusion structures to adapt their characteristics to optimize performance for different logic functions.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentEP3011593B1Method and apparatus for a diffusion bridged cell library
Publication Date: 2017.08.16 QUALCOMM INC
  • EP3011593B1 patent drawingFigure 1
  • EP3011593B1 patent drawingFigure 2
  • EP3011593B1 patent drawingFigure 3

AI summary

A library of cells for designing an integrated circuit, the library comprises continuous diffusion compatible (CDC) cells. A CDC cell includes a p-doped diffusion region electrically connected to a supply rail and continuous from the left edge to the right edge of the CDC cell; a first polysilicon gate disposed above the p-doped diffusion region and electrically connected to the p-doped diffusion region; an n-doped diffusion region electrically connected to a ground rail and continuous from the left edge to the right edge; a second polysilicon gate disposed above the n-doped diffusion region and electrically connected to the n-doped diffusion region; a left floating polysilicon gate disposed over the p-doped and n-doped diffusion regions and proximal to the left edge; and a right floating polysilicon gate disposed over the p-doped and n-doped diffusion regions and proximal to the right edge.