Clock Domain Check Reducing Pseudo Errors

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Solution Overview

Problem

Conventional clock-domain-crossing (CDC) check methods generate a large number of pseudo errors, making it difficult to distinguish real errors from irrelevant ones, which prolongs error analysis and increases production costs.

Innovation Solution

A method that uses a stationary signal with a fixed logic value to propagate through the circuit, identifying combinations of asynchronous transfers and excluding synchronization circuits, thereby reducing pseudo errors by determining appropriate circuit configurations for asynchronous transfers.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional CDC check method is used, then comprehensive error detection is achieved, but enormous amount of pseudo errors are generated

Engineering Contradiction:
Improveerror detection capabilityVSAvoidnumber of errors output
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The patent segments the error detection process into two distinct phases: (1) extraction of asynchronous transfer paths using stationary signals, and (2) verification of synchronization circuit appropriateness. This segmentation allows the system to first identify only the relevant asynchronous paths rather than reporting all potential errors, thereby reducing pseudo errors while maintaining comprehensive error detection capability.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent performs preliminary action by propagating stationary signals through the circuit before the actual CDC check to pre-identify asynchronous transfer paths. This preliminary identification step filters out synchronous transfers that would generate pseudo errors, so that the subsequent error detection focuses only on genuine asynchronous transfers requiring synchronization verification.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If comprehensive CDC check is performed, then all potential errors are detected, but error analysis time is significantly prolonged

Engineering Contradiction:
Improveerror detection coverageVSAvoiderror analysis time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent divides the error analysis workload into two segments: (1) automated extraction of asynchronous transfer paths using stationary signal propagation, and (2) focused verification only on identified asynchronous paths. This segmentation reduces the time-consuming review of pseudo errors while maintaining comprehensive error detection coverage.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent extracts only the essential asynchronous transfer paths from the entire circuit using stationary signal propagation, separating them from the vast number of synchronous transfers. This extraction process eliminates the need to analyze pseudo errors, significantly reducing error analysis time while preserving complete error detection coverage for genuine issues.

Inventive Principle:
Principle #2Taking out (Extraction)

3Area of stationary object

If synchronous transfers are included in CDC check, then complete circuit coverage is achieved, but pseudo errors increase

Engineering Contradiction:
Improvecircuit coverageVSAvoidpseudo errors
Core Design Contradiction:
Area of stationary objectVSObject-generated harmful factors

Solution Approach 1:

The patent performs preliminary action by propagating stationary signals through the entire circuit before the CDC check to pre-identify which transfers are truly asynchronous. This preliminary identification allows the system to include complete circuit coverage in the analysis while filtering out synchronous transfers that would generate pseudo errors, reporting only genuine asynchronous transfer issues.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS8392778B2Clock domain check method, clock domain check program, and recording medium
Publication Date: 2013.03.05 RENESAS ELECTRONICS CORP
  • US8392778B2 patent drawing
  • US8392778B2 patent drawing
  • US8392778B2 patent drawing

AI summary

To reduce pseudo errors.A stationary signal is propagated through the circuit to be checked. A combination is extracted in which different asynchronous transfers occur between a transmitting side register and a receiving side register. From the extracted combination of asynchronous transfers, a circuit to be checked is extracted, and a synchronization circuit of a plurality of signals is excluded from the circuit to be checked. A stationary signal is propagated through the circuit to be checked, for each combination among all combinations of logic values “1” and “0” of the stationary signal. It is checked whether or not there exists one asynchronous transmitting side register to which signal change can logically reach, in the combination of logic values of the stationary signal propagated. Based on the result, it is determined whether or not the circuit is appropriate as a synchronization circuit for a single-signal transfer, thereby reducing pseudo errors.