Clock Domain Crossing Delay Calibration for Metastability Control
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Solution Overview
Problem
Existing clock domain crossing (CDC) technologies introduce timing uncertainty when synchronizing signals across clock domains, which is undesirable in time-critical applications like radio distance ranging, due to the risk of metastability and the need for trigger signals to be active for multiple clock cycles.
Innovation Solution
A synchronisation system that includes a delay block with an adjustable delay period, calibrated to align logic transitions with non-active edges of the destination clock signal, reducing the risk of metastability and eliminating one-cycle uncertainty by ensuring consistent signal detection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a two-flip-flop synchroniser is used to prevent metastability propagation, then reliability is improved, but timing uncertainty increases due to the need for trigger signals to be active for multiple clock cycles
Solution Approach 1:
The patent applies preliminary action by detecting metastability conditions in advance using a detection block that monitors the output of the first flip-flop. When metastability is detected, the system prepares compensation signals before the second flip-flop samples the output, allowing proactive correction rather than reactive handling. This enables the system to maintain reliability while reducing the time the trigger signal must remain active.
Solution Approach 2:
The patent implements feedback by using a detection block that continuously monitors the output of the first flip-flop for metastability conditions. The detection block provides feedback signals to control logic that can adjust the sampling timing or activate compensation mechanisms. This closed-loop feedback system allows the synchronizer to adapt to metastability conditions in real-time, reducing timing uncertainty while maintaining reliability.
2Reliability
If the trigger signal is held active for more than one clock cycle to ensure correct transmission, then reliability is improved, but the timing precision deteriorates
Solution Approach 1:
The patent uses preliminary action by detecting the arrival of the trigger signal and preparing the destination domain circuitry in advance. The detection block identifies when the trigger signal has been correctly transmitted through the synchronizer, allowing the destination domain to prepare for the upcoming action without waiting for multiple clock cycles. This reduces the active duration needed for the trigger signal while ensuring reliable transmission.
Solution Approach 2:
The patent replaces the mechanical waiting approach (holding the trigger signal active for multiple fixed clock cycles) with an electronic detection and control system. The detection block electronically monitors signal transmission status and provides control signals to the destination domain, substituting the rigid time-based mechanism with a flexible event-based mechanism that maintains reliability while improving timing precision.
Data Source
AI summary
An electronic device comprises a synchronisation system that receives a signal clocked by a first clock signal having a first frequency and receives a second clock signal having said first frequency, but offset in phase from the first clock signal. The signal is delayed by an adjustable delay period. It is determined whether, following a logic transition in the delayed signal, the next clock edge received is an active edge or is a non-active edge. A calibration controller increases the delay period when the next clock edge is a non-active edge and maintains or decreases the delay period when the next clock edge is an active edge, or decreases the delay period when the next clock edge is an active edge and maintains or increases the delay period when the next clock edge is a non-active edge.