Reduced Latency Clock Domain Crossing Circuit Using Dual Buffer Segmentation

The patent segments the CDC circuit into two independent buffers: a dual-clock SRAM buffer for reliable data transfer and a single-clock DFF buffer for low-latency paths. This segmentation allows different data streams to use different buffers based on their latency requirements, resolving the contradiction between reliability and low latency.

The patent dynamically selects which buffer to use based on the destination clock domain's current state and data characteristics. The system can switch between the reliable dual-clock SRAM path and the fast single-clock DFF path, making the CDC circuit adaptive rather than static, thus achieving both reliability and low latency when needed.

The patent divides the CDC functionality into two separate buffer structures with different clocking schemes. The dual-clock SRAM buffer handles timing-critical paths while the single-clock DFF buffer handles less time-sensitive paths, reducing the complexity burden on any single buffer and simplifying the overall control logic.

The patent introduces a buffer selection mechanism that acts as an intermediary, directing data to the appropriate buffer based on timing requirements. This intermediary layer manages the complexity by providing a unified interface while internally routing to simpler or more complex buffers as needed.

The patent segments the data transfer paths into two types: high-reliability paths using dual-clock SRAM and low-latency paths using single-clock DFF buffers. By segmenting the traffic, the system can use the power-efficient single-clock path for appropriate data, reducing overall power consumption while maintaining reliability where needed.

The patent changes the clocking parameter from dual-clock to single-clock for the DFF buffer path, which reduces the dynamic power consumption associated with multiple clock distributions and synchronization logic, while still achieving acceptable reliability for non-critical data paths.

The patent segments the CDC functionality into two buffer types with different area characteristics. The dual-clock SRAM buffer provides reliable transfer for essential data while the single-clock DFF buffer provides a compact alternative for less critical data, reducing the total area required compared to using only the larger dual-clock SRAM buffers for all data.

The patent uses simpler, smaller single-clock DFF buffers for data paths where full dual-clock SRAM reliability is not required. These simpler buffers act as a compact alternative, sacrificing some reliability for significantly reduced area, which is acceptable for non-critical data paths.