CDC Laminate Structure for Inter-Metal Dielectric Defect Detection
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Solution Overview
Problem
Conventional semiconductor manufacturing processes often result in defects such as cracks and pinholes in inter-metal dielectric layers, leading to electric leakage and yield and reliability issues, necessitating effective defect detection methods.
Innovation Solution
A conducting layer-dielectric layer-conducting layer (CDC) laminate structure is designed with a dielectric layer between two conducting layers, featuring openings that create overlap regions where stress from thermal expansion mismatches can accumulate, facilitating the detection of defects in the inter-metal dielectric layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional dielectric materials are used in multi-layer metal interconnect structures, then electrical isolation is achieved, but defects such as cracks and pinholes form easily due to manufacturing complexity, leading to electric leakage and reliability issues
Solution Approach 1:
The patent applies preliminary action by forming a stress accumulation structure with openings in the dielectric layer before final manufacturing steps. This pre-configured structure with first and second openings creates predetermined stress concentration zones that will reliably indicate manufacturing defects, allowing early detection and prevention of reliability issues before chips are shipped out
2Measurement precision
If defects in the inter-metal dielectric layer are detected after chip fabrication, then yield and reliability issues are identified, but it is too late to prevent electric leakage and defects in shipped chips
Solution Approach 1:
The stress accumulation structure with openings is formed preliminarily during the manufacturing process, enabling defect detection to be performed at an intermediate stage rather than after complete fabrication. This timing allows defects to be identified and addressed before final chip assembly and shipping, preventing loss of time and reducing yield losses
3Measurement precision
If a laminate structure with overlapping metal regions and openings is used to detect defects, then defect detection capability is improved, but the device complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the detection function into separate components: first and second openings in the dielectric layer, first and second conducting layers with metal regions, and stress accumulation zones. This segmented approach creates a modular structure where each element contributes specifically to defect detection, making the complex function manageable and integrable into existing manufacturing processes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This structure allows for reliable detection of defects in the inter-metal dielectric layer, ensuring that chips produced on the same wafer do not have similar defects, thereby improving yield and reliability by enabling wafer-level testing.
Implementation Method 1
A dielectric material, also known as an inter-metal dielectric layer (IMD), is used between the multilayer metal interconnects to achieve electrical isolation
Implementation Method 2
featuring openings that create overlap regions where stress from thermal expansion mismatches can accumulate
Data Source
AI summary
The present application disclosed a conducting layer-dielectric layer-conducting layer (CDC) laminate structure and test method for detecting defects of an inter-metal dielectric layer. The laminate structure comprises: a dielectric layer formed on a substrate; a first conducting layer formed at a first side of the dielectric layer, wherein the first conducting layer includes a first metal region and at least one first opening in the first metal region; and a second conducting layer formed at a second side of the dielectric layer opposite to the first conducting layer such that the second conducting layer is separated from the first conducting layer by the dielectric layer, wherein the second conducting layer includes a second metal region and a plurality of second openings in the second metal region. The at least one first opening and the plurality of second openings are configured that a projection of the second metal region on the first conducting layer at least partially overlaps with the first metal region.