Clock Domain Crossing Metastability Verification via Circuit Graph Analysis
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Solution Overview
Problem
Current methods for verifying metastability in clock domain crossings in electronic circuits face challenges such as false violations, debuggability issues, and scalability problems, particularly due to the complexity of modern digital circuits with multiple independent clocks, leading to unpredictable behavior and potential system failures.
Innovation Solution
A method is introduced that identifies blocking values of qualifiers to determine whether metastability is present in clock domain crossings by creating a circuit graph, propagating qualifier blocking values, and performing dynamic synchronization analysis on deterministic and multiplexer gates, allowing for automatic detection of synchronized and unsynchronized crossings.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If structural verification and functional verification techniques are used for CDC verification, then metastability can be detected, but false violations and noise increase, reducing verification accuracy
Solution Approach 1:
The patent applies local quality by differentiating between control path CDCs and data path CDCs, using specialized verification methods for each type. Control path CDCs use structural verification with defined metastability analysis, while data path CDCs use protocol-dependent or protocol-independent structural analysis, optimizing verification accuracy for each specific context rather than applying a single generic method
Solution Approach 2:
The patent segments the verification process into distinct categories: control path CDC verification, data path CDC verification with protocol-dependent methods (FIFO/Handshake), and protocol-independent structural analysis. This segmentation allows each category to be verified with appropriate methods, reducing false violations by matching verification techniques to specific CDC types
2Reliability
If design tools report all CDC issues, then comprehensive verification is achieved, but debuggability decreases due to inability to identify root causes
Solution Approach 1:
The patent performs preliminary structural analysis to identify and categorize CDC issues before detailed verification. By pre-classifying CDCs as control path or data path and identifying their protocol characteristics, the system prepares verification results in advance with contextual information about root causes, making debugging easier when issues are detected
Solution Approach 2:
Instead of reporting all CDC issues uniformly and then requiring users to find root causes, the patent inverts the approach by analyzing the circuit structure first to identify root causes, then reporting issues with their causes already determined. This reverse approach makes verification results immediately actionable for debugging
3Reliability
If multiple verification methods are used to handle different CDC scenarios, then verification coverage improves, but device complexity increases
Solution Approach 1:
The patent creates a universal verification framework that handles multiple CDC scenarios through a single integrated system. The structural verification engine can analyze both control path and data path CDCs, and can operate in protocol-dependent or protocol-independent modes, providing multi-functionality without requiring separate verification tools for each CDC type
Solution Approach 2:
The patent combines multiple verification approaches into a composite verification system that integrates structural verification, protocol-dependent analysis, and protocol-independent analysis. This composite approach unifies diverse verification methods into a single coherent system, managing complexity through integration rather than multiplication of separate tools
4Reliability
If functional verification is performed with verification engines, then CDC properties can be verified, but productivity decreases due to non-conclusive properties and abstraction
Solution Approach 1:
The patent performs preliminary structural analysis to determine CDC synchronization properties before functional verification. By pre-identifying whether CDCs are synchronized or unsynchronized through structural examination, the system avoids performing exhaustive functional verification on obviously safe paths, improving productivity while maintaining verification reliability
Solution Approach 2:
The patent extracts and analyzes the structural characteristics of CDCs separately from functional verification. By taking out the structural analysis component and performing it independently, the system can quickly identify obvious metastability issues without requiring lengthy functional simulation, improving verification efficiency while maintaining thoroughness where needed
Data Source
AI summary
The technology disclosed relates to verifying metastability for a clock domain crossing (CDC) in a circuit design. The technology disclosed may include, for a destination clock domain in the circuit design, creating a circuit graph based, at least in part, on the circuit design. The circuit graph includes start points and stop points. The start points may be data inputs, clocks, and enables of the destination clock domain. The stop points may be synchronizer outputs of the destination clock domain and a source clock domain in the circuit design. The technology disclosed may also include traversing the circuit graph to mark all graph nodes that reside in a source-destination path of the CDC. Based on the marked graph nodes, the start points, and the stop points, the technology disclosed may also include propagating destination domain qualifiers on the circuit graph within an allowed sequential depth.