Asynchronous Clock Domain Verification via Signal Change Detection
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Solution Overview
Problem
Conventional CDC simulation methods face inefficiencies and omissions in verifying the operation of reception-side circuit elements due to differences in clock frequencies between transmission and reception sides, leading to incomplete verification and increased design time.
Innovation Solution
A verification support program that detects signal changes across clock domains, inputs random logic values at specific detection times, and outputs operation results to ensure comprehensive verification of meta-stable states without bias.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional CDC simulation methods are used to verify reception-side circuit elements, then verification can be performed, but verification completeness deteriorates due to omissions when transmission-side clock frequency is shorter than reception-side clock frequency
Solution Approach 1:
The verification support apparatus performs preliminary detection of all signal changes from transmission-side circuit elements during one clock cycle before the reception-side clock rises. It then proactively inputs detected signal changes to reception-side circuit elements at appropriate timings, ensuring complete verification coverage before the design period ends.
Solution Approach 2:
The apparatus continuously monitors signal changes from transmission-side circuit elements and uses this feedback to dynamically determine when to input signals to reception-side circuit elements. This feedback mechanism ensures that all signal changes are captured and verified, eliminating omissions in the verification process.
2Productivity
If conventional CDC simulation methods are used, then verification process is simple, but verification efficiency deteriorates due to repeated simulations required to reflect all signal changes
Solution Approach 1:
The verification support apparatus merges multiple verification steps into a single integrated process. It simultaneously detects signal changes, determines input timings, and inputs signals to reception-side circuit elements all within one simulation cycle, eliminating the need for repeated simulations and significantly improving verification efficiency.
Solution Approach 2:
The apparatus performs multiple functions within a single verification process: detecting signal changes from transmission-side elements, determining optimal input timings based on reception-side clock phases, and inputting signals to reception-side elements. This multi-functionality consolidates what would otherwise require multiple separate simulation steps.
3Reliability
If only the output signal from transmission-side circuit element immediately before rising edge is input, then verification process is simple, but verification coverage deteriorates due to omission of other signal changes
Solution Approach 1:
The verification support apparatus segments the verification process into distinct phases: detecting signal changes from transmission-side circuit elements, determining which signal changes need to be input, and inputting signals at appropriate timings. This segmentation allows comprehensive verification of all signal changes while maintaining clear, manageable verification steps.
Solution Approach 2:
The apparatus dynamically adjusts the verification process based on actual signal changes detected during simulation. Instead of using a fixed verification approach, it adapts its behavior to capture and verify all signal changes that occur, ensuring comprehensive coverage while maintaining operational simplicity through automated decision-making.
Data Source
AI summary
A computer-readable, non-transitory medium stores a program that causes a computer to execute detecting in a circuit-under-test, a change in a signal output from each circuit element on a transmission-side, during one clock cycle on a reception-side at an asynchronous location; inputting to each circuit element on the reception-side, a signal for which a change is not detected at a detection time among detection times when a signal change is detected at the detecting and replacing with a random logic value, a signal for which a change has been detected at a detection time among the detection times and inputting the random logic value to each circuit element on the reception-side, in an action triggered by a rising edge of an operation clock on the reception-side after the one clock cycle; and outputting for each circuit element on the reception-side, an operation result obtained based on input at the inputting.