Clock Domain Crossing Verification Apparatus for Metastable State Analysis
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Solution Overview
Problem
The verification of semiconductor integrated circuits is challenging due to metastable states caused by clock domain crossing (CDC), which are not effectively considered in normal logic verification models, leading to malfunctions and difficulties in analyzing the cause of errors, especially when CDC jitter affects downstream circuits.
Innovation Solution
A verification support apparatus that detects inconsistencies between simulation results and expected values in circuits with clock domains, sets output values to random logic values, and identifies the cause of inconsistencies by comparing simulation results, facilitating the analysis of CDC jitter effects and reducing the time required for error analysis.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a normal FF model is used for logic verification, then verification speed is maintained, but the effect of metastable state cannot be verified
Solution Approach 1:
The verification process is divided into two distinct phases: normal logic verification using standard FF models for speed, and CDC verification using specialized CDC models for accuracy. This segmentation allows each phase to use the most appropriate model type without compromising overall verification efficiency or accuracy.
Solution Approach 2:
A CDC model acts as an intermediary component that detects changes in input signals and outputs random values during clock events when setup/hold times are violated. This intermediary mechanism enables the verification system to simulate metastable state effects without requiring complete model replacement, thus maintaining verification speed while improving accuracy.
2Reliability
If CDC model is used to simulate metastable state effect, then verification accuracy is improved, but verification time increases significantly
Solution Approach 1:
The verification system dynamically selects between normal FF models and CDC models based on the specific verification requirements. Normal models are used for standard logic verification paths, while CDC models are applied only to critical clock domain crossing points where metastable states may occur. This dynamic approach minimizes the use of time-consuming CDC models while ensuring accurate verification where needed.
Solution Approach 2:
Instead of applying CDC models throughout the entire circuit, the invention applies them locally only at specific CDC points where clock domain crossings occur. This localized application ensures metastable state verification accuracy at critical points while avoiding the performance penalty of using CDC models system-wide.
3Measurement precision
If manual debugging is performed to analyze error cause, then detailed analysis is possible, but analysis time becomes excessively long
Solution Approach 1:
The verification system incorporates automated feedback mechanisms that track and report the effects of CDC jitter through the circuit. When errors are detected, the system provides feedback information about which CDC points are likely causing the issues, enabling verification engineers to focus their manual debugging efforts on specific problem areas rather than performing exhaustive manual analysis of the entire circuit.
Solution Approach 2:
The invention creates multiple copies of the verification system with different CDC jitter seed values to generate diverse simulation results. By comparing results across multiple copies, the system can identify consistent error patterns and isolate the specific CDC points responsible for failures, significantly reducing the time required for manual error analysis.
Data Source
AI summary
A verification support apparatus includes a detecting unit that detects an inconsistency between a simulation result at an observation point in a circuit-under-test and an expected value; a setting unit that sets a portion of output values to logic values different from those of the simulation result when the detecting unit detects the inconsistency, wherein the output values are random values output from elements that receive a signal in a second clock domain that receives the signal from a first clock domain asynchronously; a comparing unit that compares the expected value and a simulation result at the observation point after the setting by the setting unit; and an identifying unit that identifies whether the portion of the output values are a cause of the inconsistency, based on a result of comparison by the comparing unit.