CDC Verification by Inter-Flip-Flop Analysis to Cut Pseudo Errors
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Solution Overview
Problem
Conventional CDC verification methods in integrated circuits suffer from high pseudo error rates, making it difficult to identify real errors and increasing processing time and cost due to the analysis of non-actual signal combinations, particularly at clock multiplexer locations.
Innovation Solution
A verification method that includes specifying observation points through logic simulation, analyzing circuit operation information, extracting verification sets, and performing CDC verification for each inter-flip-flop to reduce pseudo errors and increase processing speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If CDC verification is performed statically by combining with logic simulation, then verification coverage is improved, but the number of pseudo errors increases
Solution Approach 1:
The patent segments the verification process into two distinct phases: static CDC verification and dynamic logic simulation. By dividing the verification into separate stages with different analysis methods, the system can identify potential issues statically while filtering out pseudo errors through dynamic simulation, thus improving verification coverage without being overwhelmed by false positives
Solution Approach 2:
The patent introduces an intermediary filtering mechanism that processes the results from static CDC verification. This intermediary layer analyzes the static verification results and cross-references them with logic simulation data to distinguish between real errors and pseudo errors, thereby reducing the harmful effect of pseudo errors while maintaining comprehensive verification coverage
2Reliability
If all clock signal combinations are analyzed in CDC verification, then verification completeness is improved, but processing time increases
Solution Approach 1:
The patent performs preliminary static CDC verification before conducting full logic simulation. This preliminary action identifies potential CDC issues early in the verification process, allowing the system to focus subsequent dynamic simulation efforts on specific problem areas rather than analyzing all clock signal combinations exhaustively, thus reducing overall processing time while maintaining verification completeness
Solution Approach 2:
The patent applies partial action by performing static CDC verification on all clock signal combinations first, then using the results to guide selective dynamic simulation. Instead of performing exhaustive dynamic simulation on all possible combinations, the system performs partial dynamic verification focused on areas identified by static analysis, achieving verification completeness with reduced processing time
3Ease of operation
If CDC verification is performed without decomposing by inter-flip-flop, then verification simplicity is maintained, but error identification accuracy decreases
Solution Approach 1:
The patent segments the CDC verification by inter-flip-flop boundaries, dividing the verification process into discrete units corresponding to individual flip-flop transitions across clock domains. This segmentation maintains operational simplicity through systematic organization while significantly improving error identification accuracy by isolating and analyzing specific inter-flip-flop issues rather than treating all CDC violations as a single group
Data Source
AI summary
A verification method for an integrated circuit according to an embodiment includes: acquiring circuit operation information of an integrated circuit to be verified by a logic simulation; and analyzing the circuit operation information and extracting a verification set. The verification method according to the embodiment further includes verifying a logical operation of a location where clock domains are crossed for the verification set for each inter-flip-flop.