CDCLK PLL Reprogramming for Stable External Display Switching
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Solution Overview
Problem
Existing systems experience undesirable audio loss and display issues such as blinking or tearing when an external display is added or its configuration is modified, with current solutions either consuming excessive power or causing user disruption.
Innovation Solution
A method to dynamically adjust the display clock frequency by reprogramming the phase locked loop (PLL) without turning it off, using a divide-by-2 divider or other dividing ratios to maintain optimal frequency and prevent audio loss and display issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the display clock frequency is increased to prevent display blinking and tearing, then display stability is improved, but power consumption increases
Solution Approach 1:
The patent implements dynamic adjustment of display clock frequency based on operational conditions. The system monitors display configuration changes and externally connected displays, then adjusts the clock frequency accordingly - using higher frequencies only when necessary to prevent display artifacts, and lowering frequencies during normal operation to reduce power consumption.
Solution Approach 2:
The patent changes the display clock frequency parameter dynamically based on system state. By detecting display configuration changes and external display connections, the system adjusts the clock frequency parameter to optimal values - increasing it temporarily during transitions to prevent artifacts, then reducing it for power-efficient operation.
2Use of energy by moving object
If the display clock frequency is dynamically adjusted, then power consumption is reduced, but audio loss and display artifacts may occur during frequency transitions
Solution Approach 1:
The patent performs preliminary detection of display configuration changes and external display connections before adjusting the clock frequency. By monitoring these conditions in advance, the system can initiate frequency transitions at optimal moments and ensure proper synchronization, preventing audio loss and display artifacts during the transition process.
Solution Approach 2:
The patent implements feedback mechanisms that monitor display configuration and external display status. This feedback information is used to control the clock frequency adjustment process, ensuring that transitions occur only when appropriate and that the system responds to actual operational conditions, thereby maintaining audio and display continuity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach eliminates audio loss and display problems while saving power, allowing the system to operate efficiently with multiple external displays by maintaining optimal performance and battery life.
Implementation Method 1
A method to dynamically adjust the display clock frequency by reprogramming the phase locked loop (PLL) without turning it off
Data Source
AI summary
Upon external display configuration change, a graphics display driver or any suitable hardware or software modifies the clock frequency of the processor core (e.g., graphics processor core) display engine. The graphics display driver or any suitable hardware or software reprograms the core display clock PLL (CDCLK PLL) to a new frequency, without any dead clocks during such frequency change. A divide-by-2 divider changes the frequency of the PLL on the fly or dynamically. The technique may not require the PLL to be turned off and turned back again at all.