Epitaxial Source Drain Formation via Cyclic Deposition Etch
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Solution Overview
Problem
Existing methods for forming source and drain regions in semiconductor devices, such as MOSFETs, are not entirely satisfactory in achieving optimal performance due to limitations in carrier mobility and device performance enhancement, particularly at advanced technology nodes.
Innovation Solution
A method involving a cyclic deposition/etch (CDE) process is used to form epitaxial silicon-containing material structures in recesses of a substrate, with in-situ doping and controlled thermal budget management to enhance the formation of source and drain regions, improving dopant activation levels and device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional epitaxial deposition and etching processes are used, then manufacturing simplicity is maintained, but carrier mobility and device performance are insufficient
Solution Approach 1:
The patent applies segmentation by dividing the epitaxial formation process into multiple discrete cycles of deposition and etching. Each cycle deposits a thin epitaxial layer followed by a controlled etch to remove excess material, repeating this process to build up the source and drain regions with precise control over final thickness and morphology, thereby achieving high carrier mobility through optimized material structure
Solution Approach 2:
The patent implements periodic action through cyclic deposition/etch processes where epitaxial growth and removal operations alternate in repeated cycles. This periodic application of deposition and etching allows progressive formation of source and drain regions with controlled profiles, enabling optimization of carrier mobility while managing process complexity through systematic repetition
2Productivity
If geometry size is scaled down, then production efficiency increases, but power dissipation increases
Solution Approach 1:
The patent applies parameter changes by carefully controlling deposition temperature, pressure, and gas flow rates during epitaxial growth to form source and drain regions at scaled dimensions. By optimizing these parameters, the process achieves high production efficiency for advanced technology nodes while the resulting device structure inherently addresses power dissipation through improved carrier mobility and reduced resistance
3Manufacturing precision
If epitaxial deposition is performed without cyclic etching, then process simplicity is maintained, but dopant activation and resistivity reduction are insufficient
Solution Approach 1:
The patent applies preliminary action by performing multiple deposition/etch cycles before final doping steps. Each cycle prepares the surface and structures the material to optimize subsequent dopant incorporation, ensuring high dopant activation and resistivity reduction are achieved through pre-conditioned material surfaces and optimized structural profiles
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The CDE process results in higher dopant activation levels and improved device performance by effectively forming epitaxial silicon-containing material structures with controlled thermal budgets, addressing the limitations of existing methods and enhancing carrier mobility and device performance.
Implementation Method 1
cyclic deposition/etch (CDE) process that involves repeated epitaxial deposition and partial etching
Implementation Method 2
epitaxial deposition process
Implementation Method 3
partial etching
Data Source
AI summary
The embodiments of mechanisms for monitoring thermal budget of an etch process of a cyclic deposition/etch (CDE) process to form an epitaxially grown silicon-containing material are descried to enable and to improve process control of the material formation. The monitoring is achieved by measuring the temperature of each processed wafer as a function of process time to calculate the accumulated thermal budget (ATB) of the wafer and to compare the ATB with a reference ATB (or optimal accumulated thermal budget, OATB) to see if the processed wafer is within an acceptable range (or tolerance). The results are used to determine whether to pass the processed wafer or to reject the processed wafer.