Control Data Flow Graph Generation for Hardware Description Languages
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Solution Overview
Problem
Traditional control and data flow graph (CDFG) representations for hardware description languages (HDLs) fail to adequately capture concurrency, time semantics, and hierarchical references, limiting compiler optimizations and efficient modeling of data flow.
Innovation Solution
A method for generating a control and data flow graph for HDLs involves traversing an abstract syntax tree (AST) representation on a module-by-module basis, adding execution units with loopback sinks and sources to merge and propagate concurrent paths, and using constructs like delta delays and initial/concurrent sections to model HDL-specific behaviors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional CDFG representations are used for HDLs, then the structure is simple and well-understood, but they fail to adequately represent concurrency, time semantics, and hierarchical references
Solution Approach 1:
The patent segments the control and data flow representation by introducing distinct node types (sequence points, concurrent sections, loopback sources/sinks) and edge types (control edges, data edges, feedback edges) to model different HDL semantics. This segmentation allows accurate representation of concurrency and time semantics while maintaining a structured approach to graph construction from AST nodes.
Solution Approach 2:
The patent introduces loopback sources and loopback sinks as intermediary elements that mediate between concurrent paths and sequential control flow. These intermediaries enable the graph to represent feedback mechanisms and concurrent execution semantics without requiring complete restructuring of the traditional CDFG framework, thus balancing representation accuracy with structural familiarity.
2Reliability
If loopback sources and sinks are added to model concurrent paths, then concurrency representation improves, but the number of nodes and edges increases
Solution Approach 1:
The patent merges multiple concurrent paths into a unified graph structure by introducing a single loopback source and loopback sink pair that consolidates feedback from multiple concurrent sections. This merging approach reduces the total number of graph elements compared to creating separate representation structures for each concurrent path, while still maintaining accurate concurrency semantics.
Solution Approach 2:
The loopback source and sink nodes serve multiple functions: they represent feedback edges, model concurrent execution, enable time semantics representation, and maintain control flow continuity. This multi-functionality reduces the need for additional specialized nodes, thereby limiting the increase in graph complexity while improving concurrency representation.
3Reliability
If module-by-module AST traversal is performed, then hierarchical references are handled accurately, but the processing time increases
Solution Approach 1:
The patent performs preliminary actions by constructing the CDFG in a bottom-up manner from leaf modules to root modules during AST traversal. This preliminary construction of sub-graphs for individual modules allows hierarchical references to be resolved efficiently, as parent modules can directly incorporate references to already-constructed child module graphs without re-traversing their ASTs.
Solution Approach 2:
The patent segments the AST traversal process into module-level independent units that can be processed separately and then composed hierarchically. Each module's CDFG is constructed independently through its own AST traversal, allowing parallel processing potential and reducing overall compilation time while maintaining accurate hierarchical reference resolution through the modular composition of graphs.
Data Source
AI summary
An example method of generating a control and data flow graph for hardware description language (HDL) code specifying a circuit design is described. The method includes traversing an abstract syntax tree (AST) representation of the HDL code having a plurality of modules on a module-by-module basis. The method further includes adding an execution unit to the control and data flow graph for each module having concurrent paths. Each execution unit includes nodes in the control and data flow graph. The nodes include a loopback sink that merges the concurrent paths and a loopback source that receives feedback from the loopback sink and propagates the feedback to the concurrent paths.