cDIMM Z-Axis Compression Connectors for Memory Scalability

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Solution Overview

Problem

Existing information handling systems using Small Outline Dual In-Line Memory Modules (SODIMMs) face inefficiencies due to high loading on memory channels, leading to lower speeds and increased power consumption, along with complex signal trace routing and congestion on printed circuit boards (PCBs), which limits their scalability and reversibility.

Innovation Solution

The implementation of Compression Dual In-Line Memory Modules (cDIMMs) with z-axis compression connectors that utilize surface contact connections to engage with metal contact elements, allowing for efficient signal conduction and reduced trace crossings, enabling higher speeds and improved scalability and reversibility.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If SODIMMs are used in information handling systems, then memory capacity can be provided, but memory channel loading becomes high leading to lower speeds and increased power consumption

Engineering Contradiction:
Improvememory capacityVSAvoidmemory access speed
Core Design Contradiction:
Quantity of substanceVSSpeed

Solution Approach 1:

The patent transitions from traditional planar memory module arrangements to a three-dimensional stacked architecture using cDIMMs. By stacking memory devices vertically and utilizing z-axis compression connectors, the system achieves higher memory capacity without increasing memory channel loading, thereby maintaining higher access speeds and reducing power consumption per unit of memory capacity.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Quantity of substance

If SODIMMs are used in information handling systems, then memory capacity can be provided, but power consumption increases due to high memory channel loading

Engineering Contradiction:
Improvememory capacityVSAvoidpower consumption
Core Design Contradiction:
Quantity of substanceVSUse of energy by moving object

Solution Approach 1:

The patent employs vertical stacking of memory devices with z-axis compression connectors to achieve higher density. This three-dimensional arrangement reduces the number of active memory channels required to support a given memory capacity, thereby lowering overall power consumption while maintaining or increasing total memory capacity.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Ease of operation

If SODIMMs are used in information handling systems, then memory can be installed, but signal trace routing becomes complex with congestion on PCBs

Engineering Contradiction:
Improvememory installationVSAvoidsignal trace routing complexity
Core Design Contradiction:
Ease of operationVSDevice complexity

Solution Approach 1:

The patent utilizes vertical stacking and z-axis compression connectors to establish electrical connections, eliminating the need for complex planar signal trace routing on PCBs. The compression connectors directly engage with contact elements on the stacked memory devices, significantly simplifying the signal path and reducing PCB trace congestion while maintaining ease of memory installation and replacement.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS11321009B2System and method for compression dual in-line memory module scalability
Publication Date: 2022.05.03 DELL PROD LP
  • US11321009B2 patent drawing
  • US11321009B2 patent drawing
  • US11321009B2 patent drawing

AI summary

A Dual In-Line Memory Module (DIMM) includes a plurality of memory devices mounted on a circuit board of the DIMM. The memory devices are arranged to be accessed via at least two memory channels. The DIMM further includes an array of surface contact connections. Each surface contact connection is configured to be engaged with an associated contact element of a z-axis compression connector. The array of surface contact connections are arranged to conduct signals for the memory channels. The memory devices are placed upon the memory circuit board in an array of X rows of memory devices and Y columns of memory devices, where X and Y are integers. When the DIMM has a first number of the memory devices A=X1×Y1 that is less than when the DIMM has a second number of memory devices B=X2×Y2, then either X1 is less than X2, or Y1 is less than Y2.