CDMA Signal Generator Using Precomputed Spread Sequence Memory
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Solution Overview
Problem
Current signal generators for DSSS and CDMA signals require high hardware complexity and cannot efficiently generate signals for multiple standards, as each standard has unique frame formats, modulation types, and spread sequence calculations, leading to costly and cumbersome hardware configurations, especially in signal generators for development and testing purposes.
Innovation Solution
A digital signal processor is combined with a universal hardware circuit to pre-calculate and store spread sequences, allowing for the generation of DSSS and CDMA signals with a single circuit by using an image memory to look up data symbols and spread sequence bits, reducing hardware requirements and enabling efficient generation of signals across various standards.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If separate hardware is provided for each CDMA standard, then signal generation accuracy for specific standards is improved, but device complexity and hardware outlay increase significantly
Solution Approach 1:
The patent implements a universal signal generator that can handle multiple CDMA standards (IS-95, CDMA2000, WCDMA, TDD, FDD) through a single hardware platform. The system uses standardized functional blocks (frame assembly, modulation, spreading, power weighting, summation) that can be configured via software to support different standards, eliminating the need for separate hardware for each standard while maintaining signal generation accuracy.
Solution Approach 2:
The patent employs parameter-based configuration to adapt the universal hardware to different CDMA standards. By changing parameters such as frame structure, modulation type, spreading code length, and processing timing, the same hardware can generate signals for various standards. This approach allows accurate signal generation for each standard without requiring dedicated hardware designs.
2Adaptability or versatility
If hardware is designed to support multiple CDMA standards, then adaptability is improved, but device complexity and configuration difficulty increase
Solution Approach 1:
The patent divides the signal generation process into distinct functional segments (frame assembly, modulation, spreading, power weighting, summation) that can be independently configured. Each segment has specific parameters that can be adjusted to support different standards. This segmentation allows for modular configuration where each module can be optimized independently, reducing overall configuration complexity while maintaining multi-standard adaptability.
Solution Approach 2:
The patent introduces a control unit that acts as an intermediary between the user and the complex hardware configuration. The control unit receives standard-specific parameters and automatically configures the various functional blocks accordingly, shielding the user from the underlying complexity. This intermediary layer simplifies the configuration process while enabling comprehensive multi-standard support.
3Measurement precision
If separate hardware configurations are used for different standards, then signal generation precision for each standard is maintained, but productivity and development efficiency decrease
Solution Approach 1:
The patent pre-configures parameter sets for each CDMA standard that define the optimal settings for all functional blocks. These pre-configured parameter sets can be quickly loaded and activated, allowing the system to switch between standards without manual reconfiguration. This preliminary preparation maintains signal generation precision while dramatically improving productivity during development and testing phases.
Data Source
AI summary
The invention relates to a signal generator for a DSSS or CDMA signal, comprising several spread sequence memories and a digital signal processor which pre-calculates the spread sequence in an initialization phase and deposits the same in the spread sequence memory, and which supplies data symbols to an image memory in an operating phase. Each image memory contains an image table by means of which the bits of the current data symbols and at least one current bit of the spread sequence, which is sequentially read from every spread sequence memory, is imaged in at least one output value.