Interpolator CDR Circuit with Programmable Bandwidth
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional clock and data recovery (CDR) circuits have limited tracking capability and bandwidth, particularly when dealing with a wide range of data rates, due to narrow capture range of PLL and VCO, and require complex analog components that are difficult to implement in integrated circuits.
Innovation Solution
A phase interpolator-based CDR circuit with a digitally programmable divider and finite state machine that allows for adjustable update rate and step size, enabling operation over a wide range of data rates with fixed frequency, and an anti-glitch circuit to prevent clock glitches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional PLL and VCO are used in CDR circuits, then clock recovery can be achieved, but the tracking capability and bandwidth are limited due to narrow capture range
Solution Approach 1:
The patent replaces the conventional analog PLL/VCO mechanism with a digital phase interpolator-based system. The phase interpolator uses digital logic to generate multiple clock phases and select appropriate phases based on detected transitions, eliminating the narrow capture range limitation of analog VCOs and enabling programmable bandwidth and tracking capability.
Solution Approach 2:
The patent makes the CDR circuit dynamically adaptable by allowing programmable update rates and step sizes. The system can adjust its behavior based on operating conditions, enabling it to maintain optimal tracking capability across a wide bandwidth range by dynamically changing the number of steps per update and update rate.
2Adaptability or versatility
If analog components are used to achieve wide bandwidth, then tracking capability improves, but device complexity increases and integration becomes difficult
Solution Approach 1:
The patent substitutes complex analog components with digital logic circuits. The phase interpolator uses digital counters, decoders, and multiplexers to achieve functions that would require complex analog circuitry, thereby reducing device complexity while maintaining wide bandwidth capability and improving integrability.
Solution Approach 2:
The digital phase interpolator serves multiple functions: it generates multiple clock phases, selects appropriate phases based on transition detection, provides programmable update rates, and enables adjustable step sizes. This multi-functionality in a single digital block reduces overall circuit complexity compared to separate analog components.
3Speed
If fast locking capability is achieved through high update rate, then acquisition speed improves, but tracking accuracy may be reduced
Solution Approach 1:
The patent enables dynamic adjustment of the update rate and step size based on operational requirements. During acquisition, the system can use high update rates with larger step sizes for fast locking. During tracking, it can switch to lower update rates with smaller step sizes for improved accuracy, allowing optimization of both speed and precision at different operational phases.
Solution Approach 2:
The patent changes key parameters (update rate and step size) to optimize performance. By programmably adjusting these parameters, the system can achieve fast locking when needed while maintaining high tracking accuracy during steady-state operation, resolving the trade-off between speed and precision.
4Speed
If high step size is used for fast phase adjustment, then locking speed improves, but clock glitches may occur
Solution Approach 1:
The patent segments large phase adjustments into multiple smaller steps. When a large phase correction is needed, the system divides the total phase change into a sequence of smaller incremental adjustments, each implemented at a manageable step size. This prevents clock glitches while still achieving fast overall locking by performing multiple small corrections in rapid succession.
Data Source
AI summary
The present invention facilitates clock and data recovery (330,716/718) for serial data streams (317,715) by providing a mechanism that can be employed to maintain a fixed tracking capability of an interpolator based CDR circuit (300,700) at multiple data rates (e.g., 800). The present invention further provides a wide data rate range CDR circuit (300,700), yet uses an interpolator design optimized for a fixed frequency. The invention employs a rate programmable divider circuit (606,656,706) that operates over a wide range of clock and data rates (e.g., 800) to provide various phase correction step sizes (e.g., 800) at a fixed VCO clock frequency. The divider (606,656,706) and a finite state machine (FSM) (612,662,712) of the exemplary CDR circuit (600,650,700) are manually programmed based on the data rate (614,667). Alternately, the data rate may be detected from a recovered serial data stream (718) during CDR operations (on-the-fly) utilizing a frequency detection circuit (725) to automatically program the divider (706) and FSM (712) to provide CDR circuit operation at the nearest base clock rate (716).