Clock and Data Recovery Circuit Adaptive Delay Lookup
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Solution Overview
Problem
Conventional clock data recovery (CDR) circuits face challenges in high-speed burst mode communications, particularly in quickly establishing and re-acquiring timing signals due to high jitter and broadband spectral energy density, leading to increased transmission overhead and reduced effective throughput.
Innovation Solution
A CDR circuit that generates a recovered clock signal and uses adaptive delay selection based on detected bit patterns to synchronize data sampling, allowing for rapid acquisition and processing of burst-mode signals without the need for extended headers, thereby reducing bandwidth overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional PLL-based CDR circuits are used for clock recovery, then the circuit can function with extended data streams, but the settling time is excessively long for burst-mode transmission
Solution Approach 1:
The patent applies preliminary action by pre-calculating and storing optimal delay values in a lookup table based on expected jitter conditions. When burst-mode data arrives, the circuit immediately queries the lookup table and applies the pre-determined delay setting, bypassing the traditional lengthy PLL settling process. This allows the circuit to be ready for data recovery in advance, achieving rapid acquisition without sacrificing clock recovery accuracy.
2Reliability
If extended headers are added to allow CDR circuit settling, then accurate clock recovery is achieved, but transmission overhead increases and effective throughput decreases
Solution Approach 1:
The patent extracts the settling time requirement from the data transmission process by using a separate lookup table mechanism that operates independently of the data stream. The lookup table is populated during manufacturing or initialization, and during burst-mode operation, the circuit directly queries pre-computed delay values without needing extended header data. This separation eliminates the need for transmission overhead while maintaining accurate clock recovery.
3Adaptability or versatility
If the CDR circuit must re-acquire timing signal for each burst, then burst-mode transmission is supported, but the acquisition time for each burst increases latency
Solution Approach 1:
The patent applies preliminary action by pre-computing optimal delay values for various jitter conditions and storing them in a lookup table before burst-mode transmission begins. When each burst arrives, the circuit immediately queries the lookup table with the current jitter parameters and applies the pre-calculated delay setting instantaneously. This eliminates the need for time-consuming re-acquisition processes while maintaining adaptability to different burst conditions.
4Adaptability or versatility
If conventional CDR circuits are used with high jitter and broadband spectral energy density, then they can handle NRZ format data, but the jitter tolerance is insufficient leading to increased bit error rates
Solution Approach 1:
The patent applies parameter changes by dynamically adjusting the delay parameter based on detected jitter conditions. The circuit monitors the incoming data stream for jitter characteristics and queries the lookup table with these parameters to retrieve optimal delay settings. This allows the circuit to adapt to varying jitter levels and broadband spectral conditions while maintaining NRZ format compatibility and achieving high jitter tolerance with low bit error rates.
Data Source
AI summary
A clock and data recovery circuit and method are used in a digital data communications system. The circuit and method are effectively employed for high speed, burst-mode transmission and allow rapid recovery of the clock and data signals without the need for an extended header, and notwithstanding the presence of substantial timing jitter. The method adaptively selects from among three delay times for the extraction of data by identifying a frequently recurring incoming pattern in the incoming data. The delay time is selected in a manner that insures that the same pattern is present in the reconstructed, resynchronized output data.