Clock Data Recovery Circuit Built-In Self-Test Mode
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Solution Overview
Problem
The complexity of clock and data recovery (CDR) circuits in high-speed communication channels makes testing and verification difficult, as existing solutions lack efficient built-in self-test capabilities to ensure proper operation.
Innovation Solution
A CDR circuit with built-in self-test (BIST) capabilities, including a test pattern generator and checker, allows for both normal and BIST modes of operation, enabling the generation and verification of test data patterns to detect errors, and a phase-locked loop for clock recovery, facilitating system-level testing and error detection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If CDR circuit complexity increases to support high-speed communication channels, then communication capability is improved, but testing and verification difficulty increases
Solution Approach 1:
The CDR circuit performs self-testing through built-in self-test mode where the circuit tests itself by generating test patterns internally and verifying the output without requiring external testing equipment. The test pattern generator creates known test sequences that are processed through the CDR circuit, and the results are compared against expected values to verify proper operation.
Solution Approach 2:
The CDR circuit is designed to operate in multiple modes including normal operation mode and built-in self-test mode. The same circuit infrastructure serves both data recovery functions and testing functions, allowing the circuit to be universally applicable for both communication and verification purposes without requiring separate dedicated test circuits.
2Productivity
If built-in self-test capabilities are added to CDR circuits, then testing efficiency is improved, but device complexity increases
Solution Approach 1:
The CDR circuit components serve dual purposes: the data recovery circuit also functions as the test verification path, and the normal operation mode and self-test mode share the same infrastructure. This multi-functionality allows testing capabilities to be integrated without proportionally increasing overall device complexity.
Solution Approach 2:
The self-test functionality replicates the essential data path components (test pattern generator, data recovery circuit, and output comparison) in a simplified form dedicated to testing. Rather than creating entirely separate test equipment, the patent uses copied versions of the critical signal paths to enable self-verification.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The BIST capabilities allow for efficient integration into CDR circuits with minimal overhead, enabling comprehensive testing and verification of CDR circuits, ensuring reliable operation and reducing the need for external testing equipment.
Implementation Method 1
the clock recovery circuit comprises a phase locked loop circuit. In the first mode, the phase locked loop circuit performs a phase comparison of the clock signal to the input data signal, and recovers the clock signal based on the phase comparison of the clock signal to the input data signal. In the second mode, the phase locked loop circuit divides a frequency of the clock signal to generate a frequency divided clock signal, performs a phase comparison of the reference clock signal to the frequency divided clock signal, and recovers the clock signal based on the phase comparison of the reference clock signal to the frequency divided clock signal.
Data Source
AI summary
A device comprises a clock data recovery (CDR) circuit. The CDR circuit has an input node to receive an input data signal, an output node, a data recovery circuit, and a self-test circuit. The CDR circuit supports a first mode of operation and a second mode of operation. In the first mode, the CDR circuit receives the input data signal at the input node and provides the input data signal to an input of the data recovery circuit, the data recovery circuit recovers first data from the input data signal, and the CDR circuit provides the first data for output at the output node. In the second mode, the self-test circuit generates a test data pattern which is provided to the output node and looped back to the input of the data recovery circuit, the data recovery circuit recovers second data from the test data pattern, and the self-test circuit checks the second data for errors.