CDR Clock Buffer Trimming Using Histogram-Based Phase Alignment
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Solution Overview
Problem
Existing clock buffer trimming techniques in clock and data recovery systems are influenced by duty cycle distortion in the reference clock, which affects performance, especially in high-speed applications.
Innovation Solution
The method involves trimming clock buffers using a histogram of clock-like data patterns transmitted in a reduced rate mode, where the data patterns are insensitive to duty cycle distortion by utilizing only positive or negative edges of the clock period, allowing for phase adjustment of clock buffers to align with the center of data transitions, thereby avoiding duty cycle distortion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a reference clock is used to trim clock signals, then clock buffer trimming can be performed, but duty cycle distortion in the reference clock directly influences and degrades trimming performance
Solution Approach 1:
The patent introduces an intermediary mechanism - a data pattern transmitter and histogram analyzer - that mediates between the clock buffers and the trimming decision process. Instead of directly using the distorted reference clock for trimming, the system transmits data patterns through the clock buffers and analyzes the resulting eye diagram histogram to indirectly determine optimal buffer settings, thereby isolating the trimming process from direct reference clock distortion
Solution Approach 2:
The patent replaces the traditional mechanical/time-domain reference clock-based trimming method with a statistical/histogram-based approach. Instead of relying on the temporal characteristics of the reference clock signal, the system uses histogram analysis of data pattern transitions to determine clock buffer settings, substituting a statistical measurement system for the direct time-domain measurement
2Manufacturing precision
If uniformly spaced clock phases are generated for data sampling, then ideal data recovery can be achieved, but duty cycle distortion causes mismatch in clock buffers leading to non-uniform phase spacing
Solution Approach 1:
The patent implements a feedback mechanism where the histogram analysis results are fed back to adjust clock buffer settings. The system transmits data patterns, analyzes the eye diagram histogram to detect phase spacing deviations, and uses this feedback information to iteratively refine clock buffer configurations until uniform phase spacing is achieved, compensating for initial buffer mismatches
Solution Approach 2:
The patent performs preliminary characterization of clock buffer performance by transmitting data patterns and generating histograms before final operating parameters are established. This preliminary action allows the system to identify buffer mismatches and pre-adjust settings before actual high-speed data recovery operations begin
Data Source
AI summary
Clock buffers in a clock and data recovery (CDR) system are trimmed by receiving a first transmitted clock-like data pattern in a reduced rate mode, locking the CDR using the received version of the first transmitted clock-like data pattern; and receiving a second transmitted clock-like data pattern. The first transmitted clock-like data pattern is transmitted using a first rate mode and the reduced rate mode divides the first rate mode by an integer value. The second transmitted clock-like data pattern has a run-length that is an integer division of a run-length of the first transmitted clock-like data pattern. A phase of the clock buffers is adjusted using the second transmitted clock-like data pattern. The received first transmitted clock-like data pattern has edges that correspond to only positive or negative edges of the first transmitted clock-like data pattern.