CDR VCO Buffer Slew-Rate Control for Lower Loop Delay

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Solution Overview

Problem

Existing clock and data recovery devices experience significant loop delay and jitter in bang-bang loops due to delays in comparing data and clock timing and applying frequency changes, which affects jitter and timing margin.

Innovation Solution

A clock and data recovery device that includes a voltage-controlled oscillator buffer to directly adjust the slew rate of the clock output based on up and down signals from the phase detector, reducing loop delay by immediately reflecting these signals without passing through additional circuit elements.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the clock and data recovery device uses a bang-bang loop with phase detector, charge pump, and loop filter to maintain locking state, then the clock frequency can be adjusted to track data timing, but significant loop delay occurs in comparing timing and applying frequency changes

Engineering Contradiction:
Improvelocking state stabilityVSAvoidloop delay
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The invention segments the clock and data recovery device into distinct functional blocks: equalizer, phase detector, charge pump, loop filter, and voltage-controlled oscillator. This segmentation allows optimization of each block independently, particularly enabling the phase detector to directly control the voltage-controlled oscillator with minimal intermediate processing, thereby reducing overall loop delay while maintaining reliable locking state.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The equalizer performs preliminary compensation of channel loss on input data before the data enters the phase detector. This preliminary action ensures that the data signal is already optimized for timing comparison, reducing the processing time required in subsequent stages and thereby reducing the overall loop delay while maintaining locking reliability.

Inventive Principle:
Principle #10Preliminary action

2Ease of operation

If the device passes control signal through charge pump and loop filter to control voltage-controlled oscillator, then frequency adjustment is achieved, but jitter increases due to delay in applying frequency changes

Engineering Contradiction:
Improvefrequency controlVSAvoidjitter performance
Core Design Contradiction:
Ease of operationVSReliability

Solution Approach 1:

The invention extracts and eliminates unnecessary intermediate processing stages from the control signal path. By directly connecting the phase detector output to the voltage-controlled oscillator and removing redundant filtering and processing elements, the device achieves rapid frequency adjustment with minimal delay, thereby reducing jitter while maintaining ease of frequency control.

Inventive Principle:
Principle #2Taking out (Extraction)

3Measurement precision

If additional circuit elements are used in the control signal path, then frequency control precision is improved, but loop delay increases affecting timing margin

Engineering Contradiction:
Improvefrequency control precisionVSAvoidloop delay
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The invention applies local quality optimization by implementing a simplified control signal path with direct connection between critical components. The phase detector and voltage-controlled oscillator are connected with minimal intermediate elements, ensuring that the most time-critical portion of the control loop has the fastest possible response time, thereby reducing loop delay while maintaining sufficient frequency control precision through localized optimization.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS12456982B2Clock and data recovery device
Publication Date: 2025.10.28 SILICON MITUS
  • US12456982B2 patent drawing
  • US12456982B2 patent drawing
  • US12456982B2 patent drawing

AI summary

A clock and data recovery device includes an equalizer that compensates for channel loss of input data, a phase detector that compares data output from the equalizer and a fed back clock and outputs an up signal and a down signal, a charge pump that operates according to the up signal and the down signal to output a control signal, a loop filter that removes a high-frequency component included in the control signal output from the charge pump, a voltage-controlled oscillator that changes a frequency of the clock and outputs the clock according to the control signal from which the high-frequency component is removed, and a voltage-controlled oscillator buffer that adjusts a slew rate of the clock output by the voltage-controlled oscillator according to the up signal and the down signal directly received from the phase detector and transmits the clock to the phase detector.