CDR Charge Pump Timing for VCO Jitter Reduction
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Solution Overview
Problem
Existing clock and data recovery (CDR) circuits in serial data communication suffer from jitter, which affects data rates and power efficiency, as analog latency does not scale with increased data rates, leading to inefficiencies and signal integrity issues.
Innovation Solution
The proposed solution involves a CDR circuit with a slicing circuit, phase detector, voltage-controlled oscillator (VCO), and charge pump circuits that generate and adjust clock signals by comparing phase differences and supplying currents to a circuit node, with a delayed and opposite-polarity current component to settle voltage responses efficiently, reducing jitter and loop latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If a VCO-based CDR circuit is used to generate recovered clock, then the circuit can operate without an accompanying clock signal in serial data communication, but the recovered clock includes jitter which degrades signal integrity and data rates
Solution Approach 1:
The patent implements a feedback mechanism where the recovered clock signal is fed back to the VCO through a loop filter and charge pump circuit. The phase detector compares the recovered clock phase with the input data signal, and the resulting error signal adjusts the VCO frequency to minimize phase difference, thereby reducing jitter and improving signal integrity over time.
Solution Approach 2:
The patent introduces a loop filter as an intermediary component between the phase detector and the VCO. This filter mediates the control signal by filtering high-frequency noise and smoothing the voltage adjustments, which reduces jitter in the recovered clock while maintaining the ability to track phase changes in the input signal.
2Speed
If the VCO frequency is adjusted based on voltage to generate recovered clock, then the circuit can synchronize with input signal, but analog latency does not scale with increased data rates causing inefficiencies
Solution Approach 1:
The patent employs dynamic adjustment of the VCO frequency based on real-time phase detection feedback. The system continuously adapts the clock frequency to match the input signal rate, allowing the CDR circuit to scale efficiently with increased data rates without being constrained by fixed analog latency, as the control loop dynamically optimizes performance for each operating condition.
3Productivity
If charge pump circuits supply current to circuit node based on control signals, then the voltage at the node can be adjusted to control VCO frequency, but jitter and loop latency occur due to voltage fluctuations
Solution Approach 1:
The patent applies beforehand cushioning by using the loop filter to pre-smooth the control voltage before it reaches the VCO. The filter anticipates and dampens voltage fluctuations and noise in the control signal, providing a stable voltage to the VCO that minimizes frequency jitter and improves overall circuit reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces VCO-induced jitter, enhances signal integrity, and improves power efficiency, allowing for higher data rates and robust inter-chip serial data communication by reshaping the jitter transfer function and minimizing energy spread at the circuit node.
Implementation Method 1
a voltage-controlled oscillator configured to adjust a frequency of the first and second clock signals based on a voltage of the circuit node
Implementation Method 2
a first charge pump circuit and a second charge pump circuit. In various embodiments, the first charge pump circuit may be configured to supply a first current to a circuit node based on the first and second control signals
Data Source
AI summary
Techniques are disclosed relating to clock and data recovery circuitry. In some embodiments, a slicing circuit may be configured to sample an input signal to generate a first and second sampled data signal. In some embodiments, a phase detector circuit may be configured to compare the phases of the first and second sampled data signals. In some embodiments, a first charge pump may be configured to supply a first current to a circuit node, and a second charge pump may be configured to supply a second current to the circuit node. In some embodiments, a voltage-controlled oscillator may be configured to adjust a frequency of first and second clock signals based on a voltage of the circuit node.