CDR Clock Generation Using Dithered Accumulator Tuning
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Solution Overview
Problem
Electronic systems, such as transceivers, face challenges in generating multiple clock signals of various frequencies for effective clock and data recovery, as existing systems rely on a fixed crystal frequency and lack diversity in clock signals, limiting data rate compatibility and processing efficiency.
Innovation Solution
A dithering circuit and accumulator system that repeatedly switches between values to generate a tuning word at a first clock frequency from a CDR system, and adds this tuning word to previous accumulator output values at a second clock frequency from a crystal oscillator, enabling the generation of multiple clock signals synchronized with data streams.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a fixed crystal frequency is used for clock generation, then system stability is maintained, but clock signal diversity and data rate compatibility are limited
Solution Approach 1:
The patent implements a dynamically adjustable clock generation system where the crystal oscillator frequency can be modified through variable frequency division. The system uses a programmable divider that can divide the crystal frequency by different integers (N), allowing the output clock frequency to be dynamically adjusted based on data rate requirements while maintaining the stable crystal reference
Solution Approach 2:
The system changes the frequency parameter of the clock signal by varying the division ratio N in the frequency divider circuit. By programmably changing the division factor, the output clock frequency can be adapted to different data rates without changing the physical crystal oscillator, thus achieving parameter flexibility while maintaining hardware simplicity
2Productivity
If multiple clock signals of various frequencies are generated, then data rate compatibility and processing efficiency are enhanced, but system complexity increases
Solution Approach 1:
The patent creates a universal clock generation system where a single crystal oscillator combined with a programmable frequency divider can generate multiple clock frequencies. This multi-functional approach allows the same hardware infrastructure to serve multiple data rate requirements, eliminating the need for separate oscillators for each frequency and thereby reducing overall system complexity while maintaining high productivity
3Measurement precision
If clock signals are synchronized with data streams through CDR system, then data recovery accuracy is improved, but clock signal diversity is reduced
Solution Approach 1:
The system performs preliminary frequency division and clock generation before the CDR process. By pre-generating divided clock frequencies from the crystal oscillator, the system provides diverse clock signals that can be selectively used in the CDR circuit, allowing the CDR to achieve accurate data recovery while the preliminary frequency division maintains clock diversity
Data Source
AI summary
A clock and data recovery (CDR) system may use one or more clock signals in sync with recovered data rate. By accumulating a dithering tuning counter value at a data oversampling rate, a plurality of single bit signals at multiples of the recovered data rate and in sync with the recovered data rate can be accurately generated while utilizing the full range of the accumulator. This plurality of clock signals can be used in various modules in the CDR system and other modules in a transceiver system incorporating the CDR system.