CDR Clock Alignment Using Duplicate Sampling for Optimal Phase Detection
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Solution Overview
Problem
Conventional Clock and Data Recovery (CDR) circuits in wireline transceivers face challenges in identifying optimal sampling point phases, leading to suboptimal data read accuracy, high power consumption, significant chip area occupation, and data errors, especially as data transfer rates increase.
Innovation Solution
A CDR method utilizing a duplicate clock signal to determine optimal sample point phases and a closed-loop clock alignment circuit to phase-align the primary sampling point clock signal, allowing for accurate identification of optimal sampling points without disrupting data read operations, thereby minimizing errors and reducing power consumption and chip area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional CDR circuits use mid-interval sampling point phase, then the circuit structure is simple and power consumption is low, but data read accuracy is suboptimal
Solution Approach 1:
The patent divides the clock signal generation into two separate functions: a primary sampling point clock signal for data reading and a duplicate clock signal for optimal phase identification. This segmentation allows the circuit to maintain simple operation for data reading while enabling complex optimization through the duplicate clock path without increasing overall circuit complexity.
Solution Approach 2:
The duplicate clock signal acts as an intermediary that enables optimal sampling phase identification without disrupting the primary data reading operation. By using this intermediate duplicate clock to sweep through phase ranges and identify optimal points, the system can improve measurement precision while keeping the main data path simple and unchanged.
2Measurement precision
If conventional CDR circuits perform optimal phase identification, then data read accuracy improves, but power consumption increases significantly
Solution Approach 1:
The patent segments the clock signal functionality into primary and duplicate clocks, where only the duplicate clock is used for power-intensive optimal phase identification. This allows the primary data reading operation to continue with minimal power consumption while the duplicate clock handles the optimization task separately.
Solution Approach 2:
The system creates a duplicate copy of the clock signal specifically for phase optimization purposes. This duplicate clock can be manipulated and swept through phase ranges without affecting the primary clock, allowing optimal phase identification to be performed on a copy rather than the main operational clock, thereby reducing power consumption.
3Measurement precision
If conventional CDR circuits adjust sampling point phase dynamically, then optimal sampling is achieved, but data errors increase due to disruption of data read operations
Solution Approach 1:
The patent separates data reading operations from phase optimization operations by using two distinct clock signals. The primary clock maintains a stable pre-designated phase for reliable data reading, while the duplicate clock dynamically adjusts to identify optimal phases. This segmentation prevents phase adjustments from disrupting data read operations, maintaining both accuracy and reliability.
Solution Approach 2:
The duplicate clock serves as an intermediary that performs phase optimization without directly interfering with the primary data reading clock. By conducting phase sweeps and optimizations through this intermediate duplicate signal, the system can achieve optimal sampling accuracy while the primary clock continues to provide stable, reliable data reading without disruptions.
4Measurement precision
If conventional CDR circuits implement closed-loop clock alignment, then phase alignment accuracy improves, but chip area occupation increases
Solution Approach 1:
The patent merges the optimal phase identification function and the clock alignment function into a single integrated process. The duplicate clock is used both to identify optimal phases and to provide alignment information, eliminating the need for separate dedicated alignment circuitry and reducing overall chip area while maintaining high phase alignment accuracy.
Solution Approach 2:
The duplicate clock signal performs multiple functions: it identifies optimal sampling phases, provides phase alignment information, and enables closed-loop control. By making this single duplicate clock multi-functional, the patent avoids the need for separate dedicated circuits for each function, thereby improving phase alignment accuracy without proportionally increasing chip area.
Data Source
AI summary
A CDR method/circuit utilizes a closed-loop clock alignment circuit and a duplicate clock to align a sampling point clock to both mid-interval and optimal sample point phases during data receiving processes. An initial clock is generated having the mid-interval sampling point phase, then the closed-loop clock alignment circuit generates a phase correction signal based on a phase difference between the data sampling clock and the initial clock, and then the phase correction signal is fed back to a high-speed phase mixer to adjust/align the sampling point clock to the initial clock. Subsequently, the duplicate clock is generated and utilized to determine an optimal sampling point phase while the data sampling clock is utilized to read the received data signal, and then the closed-loop clock alignment circuit is re-used to re-align the data sampling clock to the duplicate clock when the optimal sampling point phase is identified.