CDR Clock Reproduction Using N-Cycle Edge Pair Extraction
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Solution Overview
Problem
In receiver devices with clock reproduction circuits, accurately reproducing a clock signal from a received data signal is challenging due to asynchronous states and Inter-Symbol Interference (ISI) jitter, leading to erroneous or unstable lock states in the clock data recovery (CDR) circuit, especially when the data signal experiences significant attenuation at Nyquist frequency and ISI-induced radio-frequency components.
Innovation Solution
A semiconductor integrated circuit comprising a first equalizer and a clock reproduction circuit that extracts information about pairs of rise and fall edges temporarily separated by N or more clock cycles, performs phase adjustments based on this information, and uses adaptive control to adjust the boost amount of the continuous time linear equalizer (CTLE) circuit to synchronize the clock signal, ensuring accurate lock of the CDR circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the clock reproduction circuit operates in an asynchronous state with significant signal attenuation at Nyquist frequency, then the circuit can handle a wider range of input conditions, but the lock state becomes erroneous or unstable due to ISI jitter and radio-frequency components
Solution Approach 1:
The patent segments the edge detection process by identifying specific pairs of rise and fall edges that are separated by N or more clock cycles. This segmentation allows the circuit to focus on reliable edge pairs that are less affected by ISI jitter, thereby maintaining lock stability while handling asynchronous input conditions.
Solution Approach 2:
The patent implements feedback control where the clock reproduction circuit continuously monitors the lock state and adjusts its operation based on the detected edge pairs. By using the timing information from reliable edge pairs, the circuit can correct phase errors and maintain stable locking even when operating in asynchronous states with signal attenuation.
2Productivity
If the circuit uses all detected edges for clock reproduction, then the clock signal can be generated from more data, but the lock state becomes erroneous due to ISI jitter affecting edge detection accuracy
Solution Approach 1:
The patent applies local quality by selectively using only certain edge pairs (those separated by N or more clock cycles) for clock reproduction, rather than uniformly using all detected edges. This selective approach ensures that only edge pairs with sufficient temporal separation and higher timing accuracy are utilized, improving the precision of clock signal generation.
Solution Approach 2:
The patent performs preliminary filtering of edge pairs before using them for clock reproduction. By pre-identifying and selecting edge pairs that meet the N-cycle separation criterion, the circuit ensures that only high-quality edge timing information is used, thereby maintaining accurate measurement while efficiently generating the clock signal.
3Use of energy by moving object
If the CTLE circuit boost amount is increased to compensate for signal attenuation, then the received signal strength is improved, but the ISI-induced radio-frequency components increase causing CDR lock errors
Solution Approach 1:
The patent uses feedback control where the CTLE boost amount is dynamically adjusted based on the lock state of the CDR circuit. When lock errors are detected, the system reduces the boost amount to eliminate radio-frequency interference, and increases it when the lock is stable, thereby optimizing signal strength while minimizing harmful effects.
Solution Approach 2:
The patent implements dynamic adjustment of the CTLE circuit boost amount rather than using a fixed value. This dynamic control allows the system to adapt the boost level in real-time based on the detected edge pairs and CDR lock state, optimizing the balance between signal strength and interference reduction.
Data Source
AI summary
According to one embodiment, there is provided a semiconductor integrated circuit including a first equalizer and a clock reproduction circuit. The first equalizer boosts a data signal. The clock reproduction circuit extracts from the boosted data signal information of a pair consisting of a rise edge and a fall edge which are temporarily separated from each other by N or more times (N is an integer of two or higher) as much as a clock cycle, performs a phase adjustment based on the information about the pair of the rise edge and the fall edge, and reproduces a clock.