CDR Clock Extraction Using Regular Data Transitions for Jitter Resistance
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Solution Overview
Problem
High-speed serial data communication is hindered by timing shifts due to wiring delays between data and clock signals, and existing CDR circuits face challenges in maintaining high-speed operations and jitter resistance, leading to potential signal errors.
Innovation Solution
A CDR circuit configuration that includes a divider with a delay element and a latch, using a data input with regularly inserted signal transitions as a trigger for clock extraction, allowing synchronization of the input data signal with the extracted clock, and feedback control to align phases and manage jitter.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If data and clock signals are transmitted in parallel through separate wiring, then the circuit configuration is simplified, but timing shifts occur due to wiring delay differences between data and clock
Solution Approach 1:
The clock signal is extracted from the data signal itself by detecting regular transitions (rising or falling edges) in the data stream. This eliminates the need for separate clock wiring and phase synchronization, resolving the timing shift problem while maintaining simple circuit configuration.
Solution Approach 2:
The data signal serves dual purposes: it carries information and simultaneously provides the clock reference through its regular transitions. This multi-functionality eliminates the need for dedicated clock wiring and synchronization circuits.
2Manufacturing precision
If clock embedding is used to eliminate separate clock transmission, then timing shift problems are resolved, but the data transition rate must be maintained above a certain frequency for stable clock extraction
Solution Approach 1:
Regular transitions (rising or falling edges) are inserted into the data signal at predetermined intervals before transmission. This preliminary structuring ensures that the receiver can reliably extract clock information even at low data rates, as the transitions are guaranteed to occur within known time windows.
Solution Approach 2:
The data signal incorporates periodic transitions at regular intervals, creating a predictable pattern that enables stable clock extraction. This periodic structure ensures that the CDR circuit receives sufficient transition information to maintain accurate timing recovery.
3Reliability
If reference transition is inserted every certain number of bits to maintain bit transition rate, then clock extraction stability is improved, but circuit complexity increases
Solution Approach 1:
The data signal itself carries the timing information through its regular transitions, eliminating the need for separate reference clocks or complex synchronization circuits. The signal serves its own timing requirements, simplifying the overall circuit configuration while maintaining extraction stability.
4Productivity
If high-speed serial communication is implemented, then data transmission rate is improved, but timing shifts due to wiring delays become more significant
Solution Approach 1:
The regular transitions in the data signal act as an intermediary that carries timing information through the transmission channel. This intermediary mechanism allows high-speed data transmission while maintaining timing accuracy, as the transitions propagate through the same channel as the data without being affected by separate clock wiring delays.
Data Source
AI summary
Disclosed herein is a CDR circuit including delay elements, including: a divider having a delay element and configured to extract a clock by using, as a trigger, a data input with a signal transition regularly inserted; and a latch configured to latch an input data signal in synchronization with the clock extracted by the divider.