CDR Clock Alignment Using PLL Edge-Sampled Phase Control
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Solution Overview
Problem
In CDR circuits, the Phase Control Signal derived from the recovered clock domain has an arbitrary and time-changing relation to the PLL clock domain, requiring synchronization for proper utilization by the VCDL circuitry.
Innovation Solution
The synchronization is achieved by selecting an appropriate edge of the PLL clock signal as the sampling edge, allowing for coarse and fine adjustments of phase offsets, and using configuration bits to control which edge of the PLL frequency is used for phase control sampling, ensuring synchronization of phase control signals into the PLL clock domain.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If phase control signals are derived from the recovered clock domain, then the phase control can be independently adjusted relative to data sampling points, but the phase control signal has an arbitrary and time-changing relation to the PLL clock domain requiring synchronization
Solution Approach 1:
The patent introduces a synchronization mechanism that acts as an intermediary between the recovered clock domain and the PLL clock domain. This mediator aligns the phase control signals with the PLL clock edges, ensuring proper timing relationships without requiring fundamental changes to either domain's operation. The synchronization unit translates phase control information from the recovered clock domain into the PLL clock domain, resolving the timing conflict while maintaining independent phase adjustment capability.
2Adaptability or versatility
If the phase control signal changes as a function of recovered clock timing, then flexible phase adjustment is achieved, but the signal requires constant synchronization relative to the PLL clock
Solution Approach 1:
The patent implements a feedback mechanism where the synchronization status of phase control signals is continuously monitored and adjusted. The system detects timing relationships between the recovered clock and PLL clock, and dynamically adjusts the synchronization point to maintain reliable signal alignment. This feedback loop ensures that phase control flexibility is maintained while automatically compensating for timing variations, thereby ensuring signal reliability.
3Measurement precision
If coarse and fine adjustments of phase offsets are implemented, then precise phase control is achieved, but the complexity of controlling multiple adjustment levels increases
Solution Approach 1:
The patent segments the phase control mechanism into two distinct levels: coarse adjustment and fine adjustment. The coarse adjustment unit handles large phase offset changes by selecting from predefined phase steps, while the fine adjustment unit provides continuous or granular phase tuning within each coarse step. This segmentation allows precise phase control to be achieved through modular, independent control blocks, reducing overall system complexity compared to a single monolithic control mechanism.
Data Source
AI summary
The present invention synchronizes signals generated and used in different clock domains. The invention is applicable to a CDR circuit in which phase adjustment of a multiphase clock to the phase of incoming data is implemented by controlling phase offsets from the PLL frequency relative to data sampling points Si and transition sampling points Ti. In particular, these offsets are controlled by both coarse and fine adjustments.Typically CDR circuits employ feedback phase control information being supplied to the VCDL. The above described adjustments result in these phase control signals having an arbitrary and time-changing relation to the PLL clock. By properly selecting an appropriate edge of the PLL clock signal, the present invention synchronizes these phase control signals into the PLL clock domain in order to apply VCDL control in a synchronous manner.