CDR Clock Skew Adjustment for ISI-Robust High-Speed Links
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Solution Overview
Problem
In high-speed serial links, adjusting the sampling clock skew to sample data signals in the middle of the bit-time interval is challenging due to increased power consumption and channel-dependent effects like intersymbol interference (ISI), which degrades performance and is difficult to determine, especially with varying voltage and temperature conditions.
Innovation Solution
A receiver circuit that includes an analog-to-digital converter and a clock-data-recovery (CDR) error-detection circuit to generate samples and estimate ISI, with a CDR circuit modifying clock signals to reduce or eliminate ISI by associating samples with zero crossings of the communication channel's pulse response, thereby improving sampling accuracy and robustness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If baud-rate sampling is used at high data rates, then power consumption is reduced, but it becomes more difficult to adjust the skew of the sampling clock to sample data in the middle of the bit-time interval
Solution Approach 1:
The patent applies preliminary action by pre-calculating and storing optimal skew values in a lookup table before operation. The CDR circuit retrieves pre-determined skew adjustments based on detected channel conditions, eliminating the need for real-time skew optimization and making baud-rate sampling viable at high data rates without power-intensive continuous adjustment mechanisms.
Solution Approach 2:
The patent replaces mechanical/continuous adjustment mechanisms with a digital lookup table-based skew selection system. Instead of continuously varying clock skew through complex control circuits, the system substitutes a discrete selection from pre-computed optimal values, reducing power consumption while maintaining sampling accuracy at high data rates.
2Reliability
If data signals are sampled in the middle of the bit-time interval, then performance and robustness against noise and jitter are improved, but channel-dependent effects such as intersymbol interference degrade performance
Solution Approach 1:
The patent applies parameter changes by dynamically adjusting the sampling clock skew parameter based on detected channel conditions and ISI levels. The CDR circuit modifies the skew parameter to shift the sampling point away from the center when ISI is detected, optimizing the trade-off between noise robustness and ISI mitigation for each specific channel condition.
Solution Approach 2:
The patent implements feedback by continuously monitoring the data signal for signs of intersymbol interference and using this information to adjust the sampling clock skew in real-time. The CDR circuit detects ISI conditions and feeds this information back to modify the clock phase, creating a closed-loop system that adapts to channel-dependent effects while maintaining robust sampling.
3Reliability
If feed-forward equalizers are implemented to modify data signals and change data-sampling position, then performance is improved, but signal-to-noise ratio deteriorates and power consumption increases
Solution Approach 1:
The patent extracts the essential function of equalization (compensating for channel effects and ISI) from the complex feed-forward equalizer structure and implements it through a simplified CDR circuit that adjusts sampling clock skew. This extraction removes the power-intensive equalizer while retaining the beneficial effect of adapting to channel conditions through a lower-power clock adjustment mechanism.
4Adaptability or versatility
If feed-forward equalizers are implemented in receiver circuits, then data-sampling position is adjusted, but receive-circuit area increases and cost increases
Solution Approach 1:
The patent uses a simplified copying approach by implementing the equalization function through clock signal replication and phase adjustment rather than complex signal processing. The CDR circuit generates multiple clock signals with different skew values, copying the essential adaptation functionality from complex equalizers to a simpler clock-based mechanism that requires minimal additional circuit area.
Data Source
AI summary
A receiver circuit is described. In the receiver circuit, an analog-to-digital converter (ADC) generates first samples of a data signal based on a first clock signal, and a clock-data-recovery (CDR) error-detection circuit generates second samples of the data signal based on a second clock signal. In addition, the CDR error-detection circuit estimates intersymbol interference (ISI) at a current sample in the second samples from an adjacent, subsequent sample in the second samples. Based on the second samples and the estimated ISI, a CDR circuit generates the first clock signal and the second clock signal, which involves modifying the skews of either or both of these clock signals so that the current sample is associated with a zero crossing of a pulse response of a communication channel from which the data signal was received, thereby reducing or eliminating the ISI from the adjacent, subsequent sample.