CDR Control Architecture for Low-Latency Power-Saving Exit
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Solution Overview
Problem
Current electrical idle exit detection mechanisms in high-speed serial interfaces of programmable logic devices are unreliable, especially at high data rates, and fail to meet the low-latency requirements of protocols like PCI Express Gen 2 due to dependency on analog signal detection, which is not feasible for most clock data recovery (CDR) implementations.
Innovation Solution
The CDR circuitry toggles between 'lock-to-reference' and 'lock-to-data' states during the electrical idle period, with a programmable interval to minimize drift and latency, and transitions to the 'lock-to-data' state upon detection of synchronization signals, eliminating the need for analog signal detection and ensuring low-latency electrical idle exit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If analog signal detection is used to detect electrical idle exit, then the detection mechanism is simple to implement, but the reliability is poor especially at high data rates
Solution Approach 1:
The patent replaces the analog signal detection mechanism with a digital domain mechanism. Specifically, it uses a toggle signal generated by digital logic that switches between LTR and LTD states, combined with digital pattern detection of K28.7 symbols, to determine electrical idle exit. This substitution eliminates the unreliability of analog detection at high data rates while maintaining implementability through standard digital circuitry.
2Loss of time
If analog signal detection with protocol-defined voltage threshold is used, then the implementation is straightforward, but the latency to detect electrical idle exit is too long
Solution Approach 1:
The patent implements preliminary action by continuously monitoring for the specific K28.7 symbol pattern during the electrical idle period. The toggle mechanism is prepared in advance to switch states, and the digital pattern detection is continuously active, so that when data returns, the system can immediately detect the K28.7 pattern and transition states without waiting for analog signal threshold crossings, thereby reducing exit latency.
Solution Approach 2:
The patent uses digital copying of the expected K28.7 symbol pattern for comparison against the received data stream. Instead of relying on analog voltage threshold detection, the system creates a digital template of the idle pattern and uses digital logic to match incoming symbols against this template, enabling faster and more reliable detection.
3Stability of the object's composition
If the CDR toggles between LTR and LTD states with a long interval to minimize drift, then frequency stability is improved, but the latency to detect synchronization signal increases
Solution Approach 1:
The patent implements dynamic adjustment of the toggle interval based on system requirements. The toggle mechanism allows flexible configuration of the interval duration, enabling optimization between frequency stability (longer intervals) and synchronization detection speed (shorter intervals). The system can adapt the toggle timing characteristics to match specific application requirements, achieving both stability and responsiveness.
Data Source
AI summary
Clock data recovery (CDR) circuitry of a high-speed serial interface on a programmable integrated circuit device toggles, during the electrical idle period of the receiver of the interface, between its “lock-to-reference” (“LTR”) state and its normal “lock-to-data” (“LTD”) state. Whenever during this toggling mode the CDR circuitry toggles to the LTD state, it remains in that state for a predetermined interval and then returns to the LTR state, unless, while it is in the LTD state, it receives a signal from elsewhere in the receiver that data have been received and byte synchronization has occurred. The predetermined toggling interval preferably is long enough to obtain an LTR lock to minimize frequency drift, but short enough to avoid unnecessary delay in detection of the synchronization signal. Preferably, this interval is programmable by the user within limits determined by the characterization of the programmable device. Unreliable analog signal detection is thereby avoided.