Multi-Rate CDR Circuit Dead Zone Calibration for Reliable Lock
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Solution Overview
Problem
Multi-rate clock data recovery (CDR) circuits using phase detectors often lock the clock signal within a dead zone, leading to errors in data recovery and increased size and power consumption.
Innovation Solution
A CDR circuit with a phase-locked loop, multi-rate phase detector, lock detector, dead zone calibration circuit, and digital block that determines the operational rate and adjusts the phase of the multi-phase clock signal to prevent locking within the dead zone, using a charge pump current to correct phase differences.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If a multi-rate phase detector is used in a CDR circuit, then the size and power consumption are reduced, but the clock signal may be locked within a dead zone
Solution Approach 1:
The patent applies preliminary action by performing dead zone calibration before normal operation. The calibration circuit pre-adjusts the phase detector's operating point to avoid the dead zone, ensuring that when the CDR circuit enters normal data recovery mode, the clock signal is already positioned away from the dead zone, preventing locking issues while maintaining low power consumption.
Solution Approach 2:
The patent implements feedback through a calibration circuit that continuously monitors the phase detector's output and adjusts the local oscillator's frequency accordingly. This feedback mechanism detects when the clock signal approaches the dead zone and automatically corrects the frequency, maintaining reliable operation while using the efficient multi-rate phase detector architecture.
2Area of stationary object
If a multi-rate phase detector is used in a CDR circuit, then the device size is reduced, but the clock signal may be locked within a dead zone
Solution Approach 1:
The calibration circuit performs preliminary adjustment of the phase detector's operating point before normal operation begins. By pre-positioning the clock signal away from the dead zone through calibration, the compact multi-rate phase detector can operate reliably without the locking problem, achieving both small size and high reliability.
Solution Approach 2:
The patent uses feedback control where the calibration circuit monitors the phase detector output and adjusts the local oscillator frequency in real-time. This feedback ensures that the compact phase detector operates away from the dead zone, maintaining reliability while benefiting from the reduced size of the multi-rate architecture.
3Measurement precision
If the phase of the multi-phase clock signal is adjusted to prevent dead zone locking, then data recovery accuracy is improved, but additional control circuits are required
Solution Approach 1:
The patent introduces a calibration circuit as an intermediary component that mediates between the phase detector and the rest of the CDR system. This calibration circuit performs the necessary phase adjustments to avoid the dead zone without requiring complex control logic throughout the entire system, achieving improved data recovery accuracy with minimal additional complexity.
Solution Approach 2:
The patent achieves improved data recovery accuracy by changing the operating parameters of the phase detector through calibration. By adjusting the local oscillator frequency and phase detector bias points during calibration, the system optimizes performance without requiring complex real-time control circuits, simply modifying key parameters to avoid the dead zone.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Prevents clock signal locking within the dead zone, reduces errors in data recovery, and minimizes the size and power consumption of the CDR circuit compared to multi-rate voltage-controlled oscillator-based solutions.
Implementation Method 1
a phase-locked loop circuit configured to generate a multi-phase clock signal based on input data
Implementation Method 2
using a charge pump current to correct phase differences
Data Source
AI summary
A clock data recovery circuit includes a phase-locked loop circuit generating a multi-phase clock signal based on input data, the phase-locked loop circuit including a multi-rate phase detector being operable at an initial rate among a plurality of rates in an initial period; a lock detector generating a lock-enable signal by detecting a lock state of the phase-locked loop circuit; a dead zone calibration circuit determining an operational rate corresponding to a data rate of the input data among the plurality of rates in response to the lock-enable signal; and a digital block controlling the multi-rate phase detector to operate at the operational rate, and generating a calibration-enable signal. The dead zone calibration circuit determines whether the multi-phase clock signal is locked within a dead zone in response to the calibration-enable signal, and changes a phase of the multi-phase clock signal based on the multi-phase clock signal.