CDR Phase Interpolator Correction for Clock Dead-Zone Lock

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Solution Overview

Problem

Clock data recovery (CDR) circuits often become stuck in a 'dead-zone' due to distortion in data or clock signals, leading to poor data sampling as they fail to align the clock signal with the midpoint of the data eye, resulting in inefficient data recovery.

Innovation Solution

A method and circuit that utilize a controller and multiplexer to adjust phase codes input to a phase interpolator, allowing for significant phase shifts to push the CDR circuit out of the dead-zone by changing the phase code by a substantial amount, ensuring proper alignment of the clock signal with the data eye.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the CDR circuit uses conventional phase locking mechanism, then the circuit can maintain stable operation, but the circuit gets stuck in dead-zone and fails to align clock signal with data eye midpoint

Engineering Contradiction:
ImproveCDR circuit stabilityVSAvoidclock signal alignment accuracy
Core Design Contradiction:
ReliabilityVSMeasurement precision

Solution Approach 1:

The controller detects when the CDR circuit is locked and proactively calculates a corrected phase code before the dead-zone issue manifests. By performing the phase correction in advance through the multiplexer, the system prevents the clock signal from becoming misaligned with the data eye midpoint, thus maintaining both stability and precision.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The controller acts as an intermediary between the phase locked loop and the phase interpolator. It monitors the locked state and intervenes by providing corrected phase codes through the multiplexer when needed, resolving the contradiction between maintaining stable operation and achieving precise alignment without requiring changes to the core PLL mechanism.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Measurement precision

If the phase code is adjusted frequently to maintain alignment, then the clock signal can stay aligned with data eye, but the circuit complexity increases due to additional control mechanisms

Engineering Contradiction:
Improveclock signal alignment accuracyVSAvoidcontrol circuit complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The CDR circuit performs self-diagnosis by monitoring its own locked state through the phase detector. The controller uses this self-provided information to determine when correction is needed, adjusting the phase code only when the circuit is actually locked and would otherwise enter a dead-zone. This self-service approach maintains precision without requiring continuous external intervention or complex control mechanisms.

Inventive Principle:
Principle #25Self-service

3Device complexity

If the CDR circuit operates without dead-zone correction, then the device complexity remains low, but the data sampling quality deteriorates due to misalignment

Engineering Contradiction:
Improvecontrol circuit complexityVSAvoiddata sampling quality
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

Instead of continuously adjusting the phase code or implementing complex real-time correction mechanisms, the system applies partial correction only when needed - specifically when the CDR circuit is locked and at risk of entering a dead-zone. The controller makes targeted phase code adjustments through the multiplexer, providing just enough correction to maintain data sampling quality without over-engineering the control circuitry.

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS10637637B2Fixing dead-zone in clock data recovery circuits
Publication Date: 2020.04.28 QUALCOMM INC
  • US10637637B2 patent drawing
  • US10637637B2 patent drawing
  • US10637637B2 patent drawing

AI summary

A method for fixing a dead-zone in a clock and data recovery (CDR) circuit is disclosed herein. The CDR circuit includes a CDR block and a phase interpolator, the CDR block is configured to generate phase codes based on signals from a phase detector, and the phase interpolator is configured to adjust a phase of a clock signal based on the phase codes. The method includes waiting for the CDR circuit to lock, reading a first phase code from the CDR block, changing the first phase code by a first amount to obtain a second phase code, and inputting the second phase code to the phase interpolator.