CDR Delay-Cell Circuit for Precise Data-Clock Phase Alignment
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Solution Overview
Problem
Current CDR circuits in digital communication face challenges in synchronizing clock and data signals effectively, particularly in maintaining a predetermined phase relationship between the recovery data and clock signals, which affects data recovery accuracy.
Innovation Solution
The CDR circuit employs a configuration of delaying cells and oscillation delaying cells that receive and delay data and clock signals, adjusting their logic based on input signal levels to generate synchronized recovery data and clock signals, ensuring a predetermined phase relationship through equal signal delay times and shared circuit configurations, such as Gilbert cell circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a conventional CDR circuit uses an injection locking oscillator or gated oscillator to synchronize clock and data signals, then the circuit structure is relatively simple, but the phase relationship between recovery data and clock signals cannot be maintained with high precision
Solution Approach 1:
The CDR circuit is segmented into multiple delaying cells (first, second, third, fourth delaying cells) that process data and clock signals separately through distinct delay paths. Each delaying cell introduces controlled delay to its respective signal, allowing independent phase adjustment. This segmentation enables precise phase relationship control between recovery data and clock signals while maintaining a structured but manageable circuit complexity.
2Reliability
If the CDR circuit uses multiple delaying cells with equal delay times to maintain phase relationship, then synchronization accuracy is improved, but the circuit complexity increases
Solution Approach 1:
The circuit merges the data signal path and clock signal path through a symmetric structure of delaying cells. Both paths use identical delay mechanisms (delaying cells with equal delay times), creating a unified approach to phase control. This merging of similar structures achieves reliable synchronization while reducing the need for separate, complex phase adjustment mechanisms for each signal type.
Solution Approach 2:
The circuit changes the delay time parameter of each delaying cell to achieve the desired phase relationship. By adjusting the delay time parameter uniformly across all delaying cells, the circuit maintains equal delay characteristics while achieving accurate synchronization. This parameter-based control allows flexible adjustment of phase relationships without fundamentally changing the circuit architecture.
Data Source
AI summary
The CDR circuit 100 includes first to second data delaying cells ID1, ID2. The CDR circuit 100 includes first to fourth oscillation delaying cells IC1, IC2, IC3, IC4. The CDR circuit 100 outputs a second data signal d2 at a data output terminal TDout as a recovery data signal Dout. The CDR circuit 100 outputs an oscillation clock signal a0 at a clock output terminal TRCK as a recovery clock signal RCK.