CDR Circuit With Dual Proportional Paths for Complete VCO Settling

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Solution Overview

Problem

High-speed serial links face challenges in clock and data recovery (CDR) due to increased power and silicon area requirements, with existing CDR circuits experiencing incomplete settling of VCO frequency, leading to lower acquisition range and pattern-dependent proportional gain, especially in low-end CMOS technologies.

Innovation Solution

A digital clock data recovery circuit with a layered structure, utilizing multiple deserializers, vote circuits, and digital-to-analog converters (DACs) to generate and control voltage and frequency of a voltage-controlled oscillator (VCO), employing 8 UI wide pulses and majority voting to ensure complete settling and robust proportional path control.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If a single proportional path control is used in CDR circuits, then the device complexity is reduced, but the VCO settling completeness deteriorates leading to lower acquisition range

Engineering Contradiction:

ImproveCDR circuit structureVSAvoidVCO settling completeness

Core Design Contradiction:

Device complexityVSReliability

Solution Approach 1:

The single proportional path control is segmented into two separate proportional paths: an even proportional path and an odd proportional path. Each path independently controls the VCO frequency based on even or odd phase error signals respectively. This segmentation allows the VCO to settle completely for each pulse type, improving acquisition range while maintaining manageable circuit complexity through modular design.

Inventive Principle:

Principle #1Segmentation

2Reliability

If multiple proportional path controls are implemented, then VCO settling completeness is improved, but the device complexity increases

Engineering Contradiction:

ImproveVCO settling completenessVSAvoidCDR circuit structure

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The even proportional path control and odd proportional path control are merged to jointly control a single shared VCO. Both paths output control signals that are combined to adjust the same VCO frequency, achieving complete settling through coordinated control while reducing overall circuit complexity compared to having completely separate VCOs for each path.

Inventive Principle:

Principle #5Merging (Combining)

3Ease of manufacture

If traditional CDR circuits are used in low-end CMOS technologies, then manufacturing cost is reduced, but pattern-dependent proportional gain issues occur

Engineering Contradiction:

ImproveCMOS manufacturing compatibilityVSAvoidproportional gain consistency

Core Design Contradiction:

Ease of manufactureVSMeasurement precision

Solution Approach 1:

Different proportional path controls are applied locally to handle even and odd pulses differently. The even proportional path uses even phase error signals while the odd proportional path uses odd phase error signals, allowing each path to be optimized for its specific pulse type. This local differentiation eliminates pattern-dependent proportional gain issues while maintaining compatibility with low-end CMOS manufacturing processes.

Inventive Principle:

Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The proposed solution enhances CDR stability and bandwidth, achieving complete VCO settling and reducing pattern-dependent proportional gain issues, thereby improving the overall performance of high-speed serial links in low-end CMOS technologies.

Implementation Method 1

a voltage controlled oscillator (VCO) based on the even up/down signal from the first vote circuit

Methodology Applied

Scientific EffectVoltage-controlled oscillation:

Implementation Method 2

a first digital to analog converter (DAC) connected at an output of the first vote circuit and configured to control a voltage and/or frequency of a voltage controlled oscillator (VCO)

Methodology Applied

Scientific EffectDigital-to-analog conversion:

Data Source

PatentUS11870880B2Clock data recovery (CDR) with multiple proportional path controls

Publication Date: 2024.01.09 SAMSUNG DISPLAY CO LTD

AI summary

A digital clock data recovery circuit including: a first vote circuit connected at an output of a first deserializer and configured to generate an even up/down signal based on even deserialized signals from the first deserializer; a first digital to analog converter (DAC) connected at an output of the first vote circuit and configured to control a voltage and/or frequency of a voltage controlled oscillator (VCO) based on the even up/down signal from the first vote circuit; a second vote circuit connected at an output of a second deserializer and configured to generate an odd up/down signal based on odd deserialized signals from the second deserializer; and a second DAC connected at an output of the second vote circuit and configured to control the voltage and/or frequency of the VCO based on the odd up/down signal from the second vote circuit.