Clock Data Recovery Circuit Dynamic Sampling Peak Alignment
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Solution Overview
Problem
Existing clock data recovery circuits face challenges in accurately sampling input signals due to asymmetric waveforms caused by interference, leading to increased bit error rates and higher circuit complexity, as they struggle to align sampling points with peak values of the input signal.
Innovation Solution
A clock data recovery circuit that generates two sampling clocks with a phase difference greater than 0 and less than half a unit interval, allowing for dynamic adjustment to align sampling points with peak values of the input signal, thereby improving sampling accuracy and reducing bit error rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the clock samples at the center of each UI, then the phase relationship between clock and input signal is ideal, but sampling accuracy decreases when waveforms are asymmetric
Solution Approach 1:
The patent implements dynamic sampling point adjustment by comparing sampling results at different phases within each UI. The system continuously adapts the sampling point position based on waveform characteristics, transitioning from fixed center sampling to dynamic peak-aligned sampling. This resolves the contradiction by making the sampling system adaptable to asymmetric waveforms while maintaining ideal phase relationships.
Solution Approach 2:
The patent employs feedback mechanisms where sampling results are compared to determine peak value positions. The system uses the comparison between sampling points (h(τ-Tb) and h(τ+Tb)) to generate feedback that adjusts the sampling clock phase, ensuring sampling occurs at peak values rather than fixed center points. This feedback loop enables the system to adapt to waveform asymmetry while maintaining high sampling accuracy.
2Measurement precision
If more amplitude information bits are used to determine peak value position, then sampling accuracy improves, but circuit area and complexity increase
Solution Approach 1:
The patent uses partial information approach by comparing only two sampling results (h(τ-Tb) and h(τ+Tb)) rather than using full amplitude information. This partial action provides sufficient precision for peak value detection without requiring extensive amplitude bits, thereby reducing circuit complexity while maintaining adequate sampling accuracy.
Solution Approach 2:
Instead of using more amplitude information to improve precision, the patent inverts the approach by using phase comparison of sampling results. The system determines peak position through temporal relationship analysis rather than amplitude magnitude analysis, achieving precision with reduced information requirements and lower circuit complexity.
3Reliability
If sampling points are fixed at UI center, then clock phase relationship is simple, but bit error rate increases when peak values are not at center
Solution Approach 1:
The patent implements self-service by enabling the sampling system to automatically adjust its own sampling points based on detected peak value positions. The system uses its own sampling results to determine necessary phase adjustments, eliminating the need for external intervention or complex control mechanisms while reducing bit error rate through adaptive sampling.
Solution Approach 2:
The patent changes the sampling clock phase parameter dynamically based on detected waveform characteristics. By adjusting the phase parameter according to peak value positions determined from sampling comparisons, the system reduces bit error rate without requiring overly complex adjustment mechanisms, as only phase parameter modification is needed.
Data Source
AI summary
A clock data recovery method samples an input signal according to a reference clock to generate a plurality of sampling results. A first and a second sampling clocks are generated according to the reference clock. A phase difference between the two sampling clocks is larger than zero and less than half an UI and each UI corresponds to an input data. Successive UIs of the input signal are sampled according to the first and the second sampling clocks to generate a first and a second sampling results in each UI. The two sampling results are compared to generate a comparison result. An adjusting signal is generated according to the comparison result and the input data. The first and the second sampling clocks are adjusted according to the adjusting signal such that the sampling results of each UI substantially correspond to a peak value at the UI of the input signal.