Clock Data Recovery Phase Control for Eye Margin Locking
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Solution Overview
Problem
Existing clock data recovery circuits face issues with deterioration in vertical eye margin and bit error rate due to sub-optimal locking points, particularly in methods like Mueller-Muller phase detection (MMPD), which affect the timing of clock signals with high power consumption.
Innovation Solution
A clock data recovery circuit that adjusts the ratio between up and down signals using a K signal, employing a sampler and control circuit to optimize the phase of the recovered clock signal, including samplers for data sampling and error detection, and a control circuit for phase control based on these signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If Mueller-Muller phase detection (MMPD) is used for clock signal phase detection, then power consumption is reduced, but vertical eye margin deteriorates due to sub-optimal locking point
Solution Approach 1:
The patent implements dynamic adjustment of the locking point by introducing a controllable parameter K that modifies the phase detection output. The control circuit dynamically adjusts the ratio between up and down signals based on eye monitoring feedback, allowing the locking point to adapt to different operating conditions and maximize vertical eye margin while maintaining low power consumption operation
Solution Approach 2:
The patent changes the parameter K to adjust the ratio between up and down signals in the phase detection process. By modifying this parameter based on eye monitoring results, the system optimizes the locking point position to achieve maximum vertical eye margin without significantly increasing power consumption, thus resolving the contradiction between power efficiency and signal quality
2Use of energy by moving object
If Mueller-Muller phase detection (MMPD) is used, then power consumption is reduced, but bit error rate deteriorates due to sub-optimal locking point
Solution Approach 1:
The patent implements a feedback mechanism where the eye monitoring signal is fed back to the control circuit, which adjusts the parameter K accordingly. This closed-loop feedback system continuously optimizes the locking point to minimize bit error rate while maintaining low power consumption, resolving the contradiction by using feedback to adapt the detection parameters to actual signal conditions
Solution Approach 2:
The system dynamically adjusts the phase detection characteristics by modifying parameter K based on real-time eye monitoring feedback. This dynamic adaptation allows the system to optimize bit error rate performance under varying channel conditions while maintaining the low power consumption advantage of MMPD
3Reliability
If the locking point is optimized for maximum eye height, then data transmission reliability is improved, but device complexity increases due to additional control mechanisms
Solution Approach 1:
The control circuit performs multiple functions: it monitors the eye diagram using the third sampler, determines the optimal locking point position, adjusts parameter K to optimize phase detection, and generates control signals for the phase interpolator. By consolidating these functions into a single multi-functional control block, the patent achieves maximum eye height optimization without proportionally increasing device complexity
Solution Approach 2:
The patent combines the eye monitoring function, locking point optimization, and phase control into an integrated control circuit. The third sampler shares the same clock signal path as the data sampler, and the control circuit uses the eye monitoring signal to directly adjust parameter K, merging multiple functions into a unified structure that minimizes additional complexity while achieving reliable data transmission
Data Source
AI summary
A clock data recovery circuit including: a sampler to sample a comparison result between an input data signal and multiple reference voltages or to sample the input data signal based on a recovered clock signal; and a control circuit to output a control signal for controlling a phase of the recovered clock signal based on a K signal, an up signal, and a down signal.