CDR-Based Eye Width Margining for High-Speed Serial Links
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Solution Overview
Problem
High-speed serial data communication links face challenges in accurately measuring eye width and margining due to limited access with external test equipment, which degrades performance and is not suitable for all CDR architectures, especially at data rates above 10 GB/sec.
Innovation Solution
A system and method for measuring and characterizing eye width and margining using on-die circuitry, applicable to both VCO-based and PI-based CDR architectures, employing a controller module to decouple the phase detector from the loop filter, applying a margining input to shift the frequency of the margining clock signal, and counting cycles until an error is detected to determine the eye width, providing fine resolution and adaptability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If external test equipment is used to measure eye width at the receiver input terminals, then measurement capability is provided, but performance degrades and access is limited
Solution Approach 1:
The patent introduces an intermediary measurement mechanism by utilizing the existing CDR circuitry and data slicer as measurement tools. Instead of directly accessing the receiver input terminals with external equipment, the system uses the CDR's phase detector and frequency control to indirectly measure eye width through phase deviation detection, thereby avoiding performance degradation while maintaining measurement capability
Solution Approach 2:
The measurement system leverages the receiver's own internal components (CDR circuitry, phase detector, data slicer) to perform eye width measurements. The CDR's frequency control and phase detection capabilities are repurposed for measurement functions, eliminating the need for external test equipment and avoiding any additional performance degradation
2Ease of operation
If external test equipment accesses the receiver input terminals, then eye pattern measurement is enabled, but test equipment access is limited and performance degrades
Solution Approach 1:
The patent uses the CDR circuitry as an intermediary measurement interface. Instead of requiring direct access to receiver input terminals, the system incorporates measurement functionality within the existing CDR architecture, allowing measurements to be taken through the natural signal flow path without external equipment intrusion
Solution Approach 2:
The receiver performs self-measurement using its own CDR components. The phase detector and frequency control mechanisms that are already part of the receiver's operational architecture are utilized to characterize eye width, eliminating the need for external test equipment access
3Measurement precision
If conventional margining methods are used at the data slicer input, then eye opening measurement is achieved, but access is difficult in high speed links
Solution Approach 1:
The patent introduces the CDR phase detector as an intermediary measurement point. Instead of requiring direct access to the data slicer input where eye opening is traditionally measured, the system uses the phase detector's output (which reflects phase deviations related to eye width) as a remote measurement interface that is easier to access in high-speed links
Solution Approach 2:
The system uses its own CDR phase detection capability to measure eye opening characteristics. The phase detector naturally responds to timing deviations that correspond to eye width, allowing the receiver to self-characterize its eye opening without requiring external equipment access to the data slicer input
Data Source
AI summary
Generally, this disclosure describes eye width measurement and margining in communication systems. An apparatus may be configured to: decouple a phase detector from a CDR loop filter of a receiver under test in response to synchronizing a margining clock signal to a receiver clock signal; apply a margining input to the loop filter, the margining input configured to shift a frequency of the margining clock signal by a constant amount related to the margining input; compare a first bit stream and a second bit stream and configured to detect an error, the first bit stream related to a transmitted bit stream; and count cycles of the receiver clock signal or the margining clock signal, wherein an eye width associated with the receiver under test is related to the margining input, the frequency of the receiver clock signal and a count of clock cycles when the error is detected.