CDR Receiver False Lock Detection Under Sinusoidal Clock Jitter
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Solution Overview
Problem
Clock and data recovery (CDR) systems in high-speed Serializer-Deserializer (SerDes) systems often lock to incorrect frequencies due to large sinusoidal clock jitter, leading to incorrect data recovery.
Innovation Solution
A receiver circuit with a phase detector, frequency path circuit, and false lock detection circuit that detects false locking conditions and provides frequency offsets to correct the frequency path, preventing incorrect locking and ensuring true locking in the presence of periodic jitter.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the CDR frequency path periodically updates the phase interpolator to track the averaged frequency offset, then the frequency tracking capability is improved, but the system may lock to an incorrect frequency when large sinusoidal clock jitter is present
Solution Approach 1:
The patent implements a feedback mechanism where the phase detector output is monitored over multiple periods to detect false locking conditions. When false locking is detected, the system provides feedback to adjust the frequency path, preventing incorrect locking and ensuring accurate frequency tracking despite the presence of sinusoidal clock jitter.
Solution Approach 2:
The system performs preliminary detection of false locking conditions by analyzing the phase detector output over multiple periods before final locking occurs. This preliminary action allows the system to identify and correct potential false locking issues before they result in incorrect frequency lock, improving both measurement precision and reliability.
2Device complexity
If the phase detector provides only phase difference information without frequency difference information, then the circuit complexity is reduced, but the ability to distinguish true lock from false lock is impaired
Solution Approach 1:
The patent makes the phase detector output serve multiple functions: it provides phase difference information for normal CDR operation and simultaneously serves as a basis for false lock detection by analyzing the output over multiple periods. This multi-functionality allows the system to maintain simple circuit architecture while gaining false lock detection capability.
Solution Approach 2:
The system uses its own phase detector output signal to detect false locking conditions, without requiring external or additional complex measurement circuits. By analyzing the characteristics of the existing phase detector output over multiple periods, the system performs self-diagnosis of locking accuracy, reducing overall device complexity while improving detection capability.
Data Source
AI summary
A receiver circuit for receiving data is described. The receiver circuit comprises a phase detector configured to receive an input data signal; a frequency path circuit configured to receive an output of the phase detector; and a false lock detection circuit configured to receive the output of the phase detector and an output of the frequency path circuit; wherein the false lock detection circuit detects a false lock of the receiver circuit to the input data signal based upon an output of the phase detector and provides a frequency offset to the frequency path circuit. A method of receiving data is also described.