Clock Data Recovery Circuit Decoupling Feed Forward Equalizer

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Solution Overview

Problem

Current serial communication systems face challenges in decoupling the clock and data recovery (CDR) circuit from the feed-forward equalizer (FFE) to prevent sub-optimal convergence due to undesirable coupling, especially in high-oscillate low-insertion loss channels, leading to inefficiencies in signal processing and noise management.

Innovation Solution

A gradient calculator circuit is introduced to generate specific feedback signals that decouple the CDR and FFE by calculating tap coefficient gradient values, ensuring orthogonal vectors for LMS constraints, thereby preventing compensatory adaptations and maintaining optimal signal processing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If the phase detector is located after the FFE to improve signal quality, then the signal-to-noise ratio is improved, but undesirable LMS-CDR coupling occurs

Engineering Contradiction:
Improvesignal-to-noise ratioVSAvoidLMS-CDR coupling
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

A gradient calculator circuit is introduced as an intermediary component between the FFE and CDR. This gradient calculator receives the equalized signal and calculates gradient values that are then used by the CDR phase detector, thereby mediating the interaction between FFE and CDR to prevent direct coupling while maintaining improved signal quality

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The signal processing function is segmented into distinct stages: the FFE processes the input signal, the gradient calculator processes the FFE output to generate gradient values, and the CDR processes these gradients. This segmentation separates the adaptation functions of FFE and CDR, preventing coupling while allowing each to operate optimally

Inventive Principle:
Principle #1Segmentation

2Measurement precision

If the CDR input data originates from before the FFE to reduce data noise, then less noise is realized, but larger amount of data noise is realized when CDR input is from ADC

Engineering Contradiction:
Improvedata noise levelVSAvoidcoupling between CDR and FFE
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The gradient calculator serves as an intermediary that takes the equalized signal from the FFE and transforms it into gradient values for the CDR. This allows the CDR to effectively use the noise-reduced signal from the FFE without directly coupling with it, as the gradient calculator decouples the two functions

Inventive Principle:
Principle #24Intermediary (Mediator)

3Device complexity

If constant FFE main tap and tunable post-FFE slicer levels are used to reduce FFE complexity, then nonlinearity compensation is enabled, but negative coupling effects between CDR and FFE slicer adaptation increase

Engineering Contradiction:
ImproveFFE complexityVSAvoidcoupling effects
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The gradient calculator acts as a mediator that processes the output of the simplified FFE structure and provides decoupled gradient information to the CDR. This intermediary function prevents the negative coupling effects that would otherwise arise from the interaction between CDR and FFE slicer adaptation

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The system changes the parameter representation from direct signal levels to gradient values. The gradient calculator transforms the signal parameters into gradient form that is suitable for CDR processing, thereby changing the interaction mode between FFE and CDR to eliminate coupling effects

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS12034575B2Clock and data recovery circuit and feed forward equalizer decoupling
Publication Date: 2024.07.09 MELLANOX TECHNOLOGIES LTD(IL)
  • US12034575B2 patent drawing
  • US12034575B2 patent drawing
  • US12034575B2 patent drawing

AI summary

A receiver includes an analog-to-digital converter (ADC) to generate a digital output, including a set of bits corresponding to a received signal. The receiver further includes a calculator circuit coupled to the ADC, the calculator circuit to calculate a set of tap coefficient gradient values corresponding to the digital output, generate a first feedback signal corresponding to the set of tap coefficient gradient values, and generate a second feedback signal corresponding to the set of tap coefficient gradient values. The receiver further includes a clock data recovery (CDR) circuit, coupled to the calculator circuit, the CDR circuit to detect a first parameter of the received signal based on the first feedback signal. The receiver further includes a feed forward equalization (FFE) system, coupled to the calculator circuit, the FFE system including multiple filter taps having a set of filter tap coefficients to be adapted based on the second feedback signal to generate a set of adapted filter tap coefficients.