CDR Frequency Bias Correction Using Distributed Phase Steps
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing clock-data recovery (CDR) circuitry in serial data channels is limited by the slower digital clock, which restricts the speed of phase and frequency correction, and the analog overshoot effect, limiting the magnitude of corrections that can be made, particularly in applications requiring real-time response.
Innovation Solution
The implementation of a physical layer transceiver with clock-data recovery circuitry that distributes phase corrections into smaller, more frequent corrections in the analog domain, using a distribution clock slower than the digital clock, allowing multiple small corrections to be completed before the next digital clock cycle, while limiting input frequency to prevent jitter.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the digital clock speed is increased to improve correction speed, then the speed of phase and frequency correction improves, but the analog overshoot effect increases causing instability
Solution Approach 1:
The patent divides the phase correction process into multiple smaller correction steps instead of applying one large correction. The distribution circuitry breaks down the required phase adjustment into a sequence of smaller increments that are applied over multiple digital clock cycles, allowing the analog circuitry to make gradual adjustments without overshooting and causing instability.
Solution Approach 2:
The patent implements periodic correction by distributing phase adjustments across multiple periodic cycles of the digital clock. Rather than attempting to complete all corrections within a single cycle, the system applies corrections periodically over multiple cycles, which allows the analog phase rotator to settle between corrections and avoids the instability caused by rapid successive large corrections.
2Measurement precision
If the magnitude of phase correction is increased to improve alignment accuracy, then the frequency bias correction capability improves, but the analog overshoot effect increases
Solution Approach 1:
The patent segments large phase corrections into multiple smaller correction steps. The distribution circuitry calculates the total required phase correction and then distributes it across multiple smaller increments, each of which is small enough to avoid analog overshoot while collectively achieving the desired large-scale phase alignment.
Solution Approach 2:
The patent performs preliminary calculation of the total phase correction required using digital circuitry, then distributes this correction in controlled increments. The digital phase detector and distribution circuitry prepare the correction plan in advance, breaking it down into manageable steps that can be safely applied by the analog phase rotator without causing overshoot.
3Reliability
If the digital clock operates slower to reduce analog overshoot, then the analog response stability improves, but the correction speed is limited
Solution Approach 1:
The patent maintains continuous useful action by keeping the digital clock running at its normal speed while continuously distributing corrections through the distribution circuitry. The system doesn't slow down the digital clock but instead continuously applies small corrections in sequence, ensuring that phase alignment work progresses continuously without interruption while maintaining analog stability.
Solution Approach 2:
The distribution circuitry acts as an intermediary between the digital phase detector and the analog phase rotator. It translates the digital correction requirements into a sequence of smaller analog-friendly correction steps, mediating between the fast digital domain and the slower analog domain to maintain both speed and stability.
4Measurement precision
If multiple small corrections are applied in the analog domain, then the maximum correctable frequency bias increases, but the circuit complexity increases
Solution Approach 1:
The distribution circuitry performs multiple functions using a unified structure: it calculates the required phase correction, divides it into smaller steps, generates the appropriate control signals for the analog phase rotator, and manages the timing of corrections. This multi-functional approach increases capability without proportionally increasing complexity.
Solution Approach 2:
The patent replaces complex analog frequency synthesis mechanisms with a simpler digital distribution approach. Instead of using complex analog circuitry to generate multiple correction frequencies, the system uses digital logic to distribute phase corrections over time, substituting mechanical/analog complexity with digital control simplicity.
Data Source
AI summary
A physical layer transceiver for a serial data channel includes receiver circuitry having a local clock. Received signals arrive on the channel according to a remote clock. Clock-data recovery circuitry aligns the local clock with the remote clock by correcting phase and frequency error between the local and remote clocks. The clock-data recovery circuitry includes digital phase error detection circuitry operating according to a digital clock to detect phase error between the local and remote clocks, analog phase rotation circuitry to correct the detected phase error, distribution circuitry to divide the detected phase error into multiple phase error steps, and an analog clock source configured to provide the local clock to the analog phase rotation circuitry, and to provide to the distribution circuitry a distribution clock that is slower than the local clock, to correct the local clock by at least one step during one digital clock period.