CDR Frequency Detector Using Delayed Edge Logic
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Solution Overview
Problem
Existing frequency acquisition methods in clock and data recovery (CDR) systems, such as phase-frequency detectors and counter-based detectors, are not suitable for digital CDR and face challenges with low-swing signals, requiring complex multi-bit arithmetic operations and are difficult to implement.
Innovation Solution
A frequency detector circuit using a transition detector, delay circuits, and combinational logic to generate UP or DOWN signals based on edge transitions in the data input, allowing for efficient frequency detection without multi-bit arithmetic operations, and integrating with a bang-bang phase detector for accurate clock alignment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If phase-frequency detector or counter-based frequency detector is used, then frequency detection capability is provided, but device complexity and implementation difficulty increase significantly
Solution Approach 1:
The frequency detection function is segmented into three independent delay circuits (first, second, and third delay circuits) that process signal edges at different delay stages. Each delay circuit operates independently to generate delayed versions of the input signal edges, allowing the complex frequency detection task to be divided into simpler, manageable segments that can be implemented with basic logic gates rather than complex multi-bit arithmetic operations.
Solution Approach 2:
The patent introduces delay circuits as intermediary elements between the input signal and the frequency detection logic. These delay circuits act as mediators that transform the input signal into multiple delayed versions, which are then fed into simple combinational logic (AND, OR, NOT gates). This intermediary approach replaces the need for complex counter-based frequency detection with a simpler delay-based mechanism.
2Measurement precision
If multi-bit counters and arithmetic operations are used for frequency detection, then frequency measurement capability is achieved, but area and complexity requirements increase
Solution Approach 1:
The patent replaces the mechanical/computational system of multi-bit counters and arithmetic operations with an electronic signal processing system based on delay circuits and combinational logic gates. Instead of using counters that require multiple bits and arithmetic units, the invention uses a purely logical approach where delay circuits generate timed versions of the input signal and simple logic gates (AND, OR, NOT) perform the frequency detection function, significantly reducing the required circuit area.
3Measurement precision
If complex frequency acquisition circuits are used, then frequency acquisition function is provided, but ease of manufacture and implementation deteriorates
Solution Approach 1:
The patent changes the operational parameters of the frequency detection system by using variable delay times in the delay circuits instead of complex counting operations. The first, second, and third delay circuits introduce different time delays to the input signal edges, creating a time-based detection mechanism that is simpler to manufacture and implement than counter-based systems. This parameter change from arithmetic operations to time-based logic simplifies the manufacturing process and improves implementation ease.
Data Source
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Figure 2A~2B
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AI summary
A frequency detector circuit comprising: a transition detector configured to receive a data input and provide a first edge output based on transitions in the data input; a first circuit configured to generate a second edge output; a second circuit configured to generate a third edge output; and combinational logic configured to: output an UP output when at least two of the first edge output, the second edge output, and the third edge output have a first state; and output a DOWN output when the first edge output, the second edge output, and the third edge output all have a second state.